esp32p4/lp_sys/
hp_root_clk_ctrl.rs

1#[doc = "Register `HP_ROOT_CLK_CTRL` reader"]
2pub type R = crate::R<HP_ROOT_CLK_CTRL_SPEC>;
3#[doc = "Register `HP_ROOT_CLK_CTRL` writer"]
4pub type W = crate::W<HP_ROOT_CLK_CTRL_SPEC>;
5#[doc = "Field `CPU_CLK_EN` reader - clock gate enable for hp cpu root 400M clk"]
6pub type CPU_CLK_EN_R = crate::BitReader;
7#[doc = "Field `CPU_CLK_EN` writer - clock gate enable for hp cpu root 400M clk"]
8pub type CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SYS_CLK_EN` reader - clock gate enable for hp sys root 480M clk"]
10pub type SYS_CLK_EN_R = crate::BitReader;
11#[doc = "Field `SYS_CLK_EN` writer - clock gate enable for hp sys root 480M clk"]
12pub type SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bit 0 - clock gate enable for hp cpu root 400M clk"]
15    #[inline(always)]
16    pub fn cpu_clk_en(&self) -> CPU_CLK_EN_R {
17        CPU_CLK_EN_R::new((self.bits & 1) != 0)
18    }
19    #[doc = "Bit 1 - clock gate enable for hp sys root 480M clk"]
20    #[inline(always)]
21    pub fn sys_clk_en(&self) -> SYS_CLK_EN_R {
22        SYS_CLK_EN_R::new(((self.bits >> 1) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("HP_ROOT_CLK_CTRL")
29            .field("cpu_clk_en", &format_args!("{}", self.cpu_clk_en().bit()))
30            .field("sys_clk_en", &format_args!("{}", self.sys_clk_en().bit()))
31            .finish()
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for crate::generic::Reg<HP_ROOT_CLK_CTRL_SPEC> {
36    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
37        core::fmt::Debug::fmt(&self.read(), f)
38    }
39}
40impl W {
41    #[doc = "Bit 0 - clock gate enable for hp cpu root 400M clk"]
42    #[inline(always)]
43    #[must_use]
44    pub fn cpu_clk_en(&mut self) -> CPU_CLK_EN_W<HP_ROOT_CLK_CTRL_SPEC> {
45        CPU_CLK_EN_W::new(self, 0)
46    }
47    #[doc = "Bit 1 - clock gate enable for hp sys root 480M clk"]
48    #[inline(always)]
49    #[must_use]
50    pub fn sys_clk_en(&mut self) -> SYS_CLK_EN_W<HP_ROOT_CLK_CTRL_SPEC> {
51        SYS_CLK_EN_W::new(self, 1)
52    }
53}
54#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_root_clk_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_root_clk_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
55pub struct HP_ROOT_CLK_CTRL_SPEC;
56impl crate::RegisterSpec for HP_ROOT_CLK_CTRL_SPEC {
57    type Ux = u32;
58}
59#[doc = "`read()` method returns [`hp_root_clk_ctrl::R`](R) reader structure"]
60impl crate::Readable for HP_ROOT_CLK_CTRL_SPEC {}
61#[doc = "`write(|w| ..)` method takes [`hp_root_clk_ctrl::W`](W) writer structure"]
62impl crate::Writable for HP_ROOT_CLK_CTRL_SPEC {
63    type Safety = crate::Unsafe;
64    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
65    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
66}
67#[doc = "`reset()` method sets HP_ROOT_CLK_CTRL to value 0x03"]
68impl crate::Resettable for HP_ROOT_CLK_CTRL_SPEC {
69    const RESET_VALUE: u32 = 0x03;
70}
esp32p4/lp_sys/hp_root_clk_ctrl.rs

esp32p4/lp_sys/
hp_root_clk_ctrl.rs
