1#[doc = "Register `CTR` reader"]
2pub type R = crate::R<CTR_SPEC>;
3#[doc = "Register `CTR` writer"]
4pub type W = crate::W<CTR_SPEC>;
5#[doc = "Field `SDA_FORCE_OUT` reader - Configures the SDA output mode 1: Direct output, 0: Open drain output."]
6pub type SDA_FORCE_OUT_R = crate::BitReader;
7#[doc = "Field `SDA_FORCE_OUT` writer - Configures the SDA output mode 1: Direct output, 0: Open drain output."]
8pub type SDA_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SCL_FORCE_OUT` reader - Configures the SCL output mode 1: Direct output, 0: Open drain output."]
10pub type SCL_FORCE_OUT_R = crate::BitReader;
11#[doc = "Field `SCL_FORCE_OUT` writer - Configures the SCL output mode 1: Direct output, 0: Open drain output."]
12pub type SCL_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SAMPLE_SCL_LEVEL` reader - Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level. 0: Sample SDA data on the SCL high level."]
14pub type SAMPLE_SCL_LEVEL_R = crate::BitReader;
15#[doc = "Field `SAMPLE_SCL_LEVEL` writer - Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level. 0: Sample SDA data on the SCL high level."]
16pub type SAMPLE_SCL_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RX_FULL_ACK_LEVEL` reader - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold."]
18pub type RX_FULL_ACK_LEVEL_R = crate::BitReader;
19#[doc = "Field `RX_FULL_ACK_LEVEL` writer - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold."]
20pub type RX_FULL_ACK_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TRANS_START` writer - Configures to start sending the data in txfifo for slave. 0: No effect 1: Start"]
22pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `TX_LSB_FIRST` reader - Configures to control the sending order for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."]
24pub type TX_LSB_FIRST_R = crate::BitReader;
25#[doc = "Field `TX_LSB_FIRST` writer - Configures to control the sending order for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."]
26pub type TX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `RX_LSB_FIRST` reader - Configures to control the storage order for received data. 1: receive data from the least significant bit 0: receive data from the most significant bit."]
28pub type RX_LSB_FIRST_R = crate::BitReader;
29#[doc = "Field `RX_LSB_FIRST` writer - Configures to control the storage order for received data. 1: receive data from the least significant bit 0: receive data from the most significant bit."]
30pub type RX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `CLK_EN` reader - Configures whether to gate clock signal for registers. 0: Force clock on for registers 1: Support clock only when registers are read or written to by software."]
32pub type CLK_EN_R = crate::BitReader;
33#[doc = "Field `CLK_EN` writer - Configures whether to gate clock signal for registers. 0: Force clock on for registers 1: Support clock only when registers are read or written to by software."]
34pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `ARBITRATION_EN` reader - Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable"]
36pub type ARBITRATION_EN_R = crate::BitReader;
37#[doc = "Field `ARBITRATION_EN` writer - Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable"]
38pub type ARBITRATION_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `FSM_RST` writer - Configures to reset the SCL_FSM. 0: No effect 1: Reset"]
40pub type FSM_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `CONF_UPGATE` writer - Configures this bit for synchronization 0: No effect 1: Synchronize"]
42pub type CONF_UPGATE_W<'a, REG> = crate::BitWriter<'a, REG>;
43impl R {
44 #[doc = "Bit 0 - Configures the SDA output mode 1: Direct output, 0: Open drain output."]
45 #[inline(always)]
46 pub fn sda_force_out(&self) -> SDA_FORCE_OUT_R {
47 SDA_FORCE_OUT_R::new((self.bits & 1) != 0)
48 }
49 #[doc = "Bit 1 - Configures the SCL output mode 1: Direct output, 0: Open drain output."]
50 #[inline(always)]
51 pub fn scl_force_out(&self) -> SCL_FORCE_OUT_R {
52 SCL_FORCE_OUT_R::new(((self.bits >> 1) & 1) != 0)
53 }
54 #[doc = "Bit 2 - Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level. 0: Sample SDA data on the SCL high level."]
55 #[inline(always)]
56 pub fn sample_scl_level(&self) -> SAMPLE_SCL_LEVEL_R {
57 SAMPLE_SCL_LEVEL_R::new(((self.bits >> 2) & 1) != 0)
58 }
59 #[doc = "Bit 3 - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold."]
60 #[inline(always)]
61 pub fn rx_full_ack_level(&self) -> RX_FULL_ACK_LEVEL_R {
62 RX_FULL_ACK_LEVEL_R::new(((self.bits >> 3) & 1) != 0)
63 }
64 #[doc = "Bit 6 - Configures to control the sending order for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."]
65 #[inline(always)]
66 pub fn tx_lsb_first(&self) -> TX_LSB_FIRST_R {
67 TX_LSB_FIRST_R::new(((self.bits >> 6) & 1) != 0)
68 }
69 #[doc = "Bit 7 - Configures to control the storage order for received data. 1: receive data from the least significant bit 0: receive data from the most significant bit."]
70 #[inline(always)]
71 pub fn rx_lsb_first(&self) -> RX_LSB_FIRST_R {
72 RX_LSB_FIRST_R::new(((self.bits >> 7) & 1) != 0)
73 }
74 #[doc = "Bit 8 - Configures whether to gate clock signal for registers. 0: Force clock on for registers 1: Support clock only when registers are read or written to by software."]
75 #[inline(always)]
76 pub fn clk_en(&self) -> CLK_EN_R {
77 CLK_EN_R::new(((self.bits >> 8) & 1) != 0)
78 }
79 #[doc = "Bit 9 - Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable"]
80 #[inline(always)]
81 pub fn arbitration_en(&self) -> ARBITRATION_EN_R {
82 ARBITRATION_EN_R::new(((self.bits >> 9) & 1) != 0)
83 }
84}
85#[cfg(feature = "impl-register-debug")]
86impl core::fmt::Debug for R {
87 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
88 f.debug_struct("CTR")
89 .field(
90 "sda_force_out",
91 &format_args!("{}", self.sda_force_out().bit()),
92 )
93 .field(
94 "scl_force_out",
95 &format_args!("{}", self.scl_force_out().bit()),
96 )
97 .field(
98 "sample_scl_level",
99 &format_args!("{}", self.sample_scl_level().bit()),
100 )
101 .field(
102 "rx_full_ack_level",
103 &format_args!("{}", self.rx_full_ack_level().bit()),
104 )
105 .field(
106 "tx_lsb_first",
107 &format_args!("{}", self.tx_lsb_first().bit()),
108 )
109 .field(
110 "rx_lsb_first",
111 &format_args!("{}", self.rx_lsb_first().bit()),
112 )
113 .field("clk_en", &format_args!("{}", self.clk_en().bit()))
114 .field(
115 "arbitration_en",
116 &format_args!("{}", self.arbitration_en().bit()),
117 )
118 .finish()
119 }
120}
121#[cfg(feature = "impl-register-debug")]
122impl core::fmt::Debug for crate::generic::Reg<CTR_SPEC> {
123 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
124 core::fmt::Debug::fmt(&self.read(), f)
125 }
126}
127impl W {
128 #[doc = "Bit 0 - Configures the SDA output mode 1: Direct output, 0: Open drain output."]
129 #[inline(always)]
130 #[must_use]
131 pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<CTR_SPEC> {
132 SDA_FORCE_OUT_W::new(self, 0)
133 }
134 #[doc = "Bit 1 - Configures the SCL output mode 1: Direct output, 0: Open drain output."]
135 #[inline(always)]
136 #[must_use]
137 pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<CTR_SPEC> {
138 SCL_FORCE_OUT_W::new(self, 1)
139 }
140 #[doc = "Bit 2 - Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level. 0: Sample SDA data on the SCL high level."]
141 #[inline(always)]
142 #[must_use]
143 pub fn sample_scl_level(&mut self) -> SAMPLE_SCL_LEVEL_W<CTR_SPEC> {
144 SAMPLE_SCL_LEVEL_W::new(self, 2)
145 }
146 #[doc = "Bit 3 - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold."]
147 #[inline(always)]
148 #[must_use]
149 pub fn rx_full_ack_level(&mut self) -> RX_FULL_ACK_LEVEL_W<CTR_SPEC> {
150 RX_FULL_ACK_LEVEL_W::new(self, 3)
151 }
152 #[doc = "Bit 5 - Configures to start sending the data in txfifo for slave. 0: No effect 1: Start"]
153 #[inline(always)]
154 #[must_use]
155 pub fn trans_start(&mut self) -> TRANS_START_W<CTR_SPEC> {
156 TRANS_START_W::new(self, 5)
157 }
158 #[doc = "Bit 6 - Configures to control the sending order for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."]
159 #[inline(always)]
160 #[must_use]
161 pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<CTR_SPEC> {
162 TX_LSB_FIRST_W::new(self, 6)
163 }
164 #[doc = "Bit 7 - Configures to control the storage order for received data. 1: receive data from the least significant bit 0: receive data from the most significant bit."]
165 #[inline(always)]
166 #[must_use]
167 pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<CTR_SPEC> {
168 RX_LSB_FIRST_W::new(self, 7)
169 }
170 #[doc = "Bit 8 - Configures whether to gate clock signal for registers. 0: Force clock on for registers 1: Support clock only when registers are read or written to by software."]
171 #[inline(always)]
172 #[must_use]
173 pub fn clk_en(&mut self) -> CLK_EN_W<CTR_SPEC> {
174 CLK_EN_W::new(self, 8)
175 }
176 #[doc = "Bit 9 - Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable"]
177 #[inline(always)]
178 #[must_use]
179 pub fn arbitration_en(&mut self) -> ARBITRATION_EN_W<CTR_SPEC> {
180 ARBITRATION_EN_W::new(self, 9)
181 }
182 #[doc = "Bit 10 - Configures to reset the SCL_FSM. 0: No effect 1: Reset"]
183 #[inline(always)]
184 #[must_use]
185 pub fn fsm_rst(&mut self) -> FSM_RST_W<CTR_SPEC> {
186 FSM_RST_W::new(self, 10)
187 }
188 #[doc = "Bit 11 - Configures this bit for synchronization 0: No effect 1: Synchronize"]
189 #[inline(always)]
190 #[must_use]
191 pub fn conf_upgate(&mut self) -> CONF_UPGATE_W<CTR_SPEC> {
192 CONF_UPGATE_W::new(self, 11)
193 }
194}
195#[doc = "Transmission setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
196pub struct CTR_SPEC;
197impl crate::RegisterSpec for CTR_SPEC {
198 type Ux = u32;
199}
200#[doc = "`read()` method returns [`ctr::R`](R) reader structure"]
201impl crate::Readable for CTR_SPEC {}
202#[doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"]
203impl crate::Writable for CTR_SPEC {
204 type Safety = crate::Unsafe;
205 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
206 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
207}
208#[doc = "`reset()` method sets CTR to value 0x0208"]
209impl crate::Resettable for CTR_SPEC {
210 const RESET_VALUE: u32 = 0x0208;
211}