esp32p4/isp/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `ISP_DATA_TYPE_ERR_INT_CLR` writer - write 1 to clear input data type error"]
4pub type ISP_DATA_TYPE_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `ISP_ASYNC_FIFO_OVF_INT_CLR` writer - write 1 to clear isp input fifo overflow"]
6pub type ISP_ASYNC_FIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `ISP_BUF_FULL_INT_CLR` writer - write 1 to clear isp input buffer full"]
8pub type ISP_BUF_FULL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ISP_HVNUM_SETTING_ERR_INT_CLR` writer - write 1 to clear hnum and vnum setting format error"]
10pub type ISP_HVNUM_SETTING_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR_INT_CLR` writer - write 1 to clear setting invalid reg_data_type"]
12pub type ISP_DATA_TYPE_SETTING_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ISP_MIPI_HNUM_UNMATCH_INT_CLR` writer - write 1 to clear hnum setting unmatch with mipi input"]
14pub type ISP_MIPI_HNUM_UNMATCH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `DPC_CHECK_DONE_INT_CLR` writer - write 1 to clear dpc check done"]
16pub type DPC_CHECK_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `GAMMA_XCOORD_ERR_INT_CLR` writer - write 1 to clear gamma setting error"]
18pub type GAMMA_XCOORD_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `AE_MONITOR_INT_CLR` writer - write 1 to clear ae monitor"]
20pub type AE_MONITOR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `AE_FRAME_DONE_INT_CLR` writer - write 1 to clear ae"]
22pub type AE_FRAME_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `AF_FDONE_INT_CLR` writer - write 1 to clear af statistic"]
24pub type AF_FDONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `AF_ENV_INT_CLR` writer - write 1 to clear af monitor"]
26pub type AF_ENV_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `AWB_FDONE_INT_CLR` writer - write 1 to clear awb"]
28pub type AWB_FDONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `HIST_FDONE_INT_CLR` writer - write 1 to clear histogram"]
30pub type HIST_FDONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `FRAME_INT_CLR` writer - write 1 to clear isp frame end"]
32pub type FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `BLC_FRAME_INT_CLR` writer - write 1 to clear blc frame done"]
34pub type BLC_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `LSC_FRAME_INT_CLR` writer - write 1 to clear lsc frame done"]
36pub type LSC_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `DPC_FRAME_INT_CLR` writer - write 1 to clear dpc frame done"]
38pub type DPC_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `BF_FRAME_INT_CLR` writer - write 1 to clear bf frame done"]
40pub type BF_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `DEMOSAIC_FRAME_INT_CLR` writer - write 1 to clear demosaic frame done"]
42pub type DEMOSAIC_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
43#[doc = "Field `MEDIAN_FRAME_INT_CLR` writer - write 1 to clear median frame done"]
44pub type MEDIAN_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `CCM_FRAME_INT_CLR` writer - write 1 to clear ccm frame done"]
46pub type CCM_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `GAMMA_FRAME_INT_CLR` writer - write 1 to clear gamma frame done"]
48pub type GAMMA_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `RGB2YUV_FRAME_INT_CLR` writer - write 1 to clear rgb2yuv frame done"]
50pub type RGB2YUV_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
51#[doc = "Field `SHARP_FRAME_INT_CLR` writer - write 1 to clear sharp frame done"]
52pub type SHARP_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `COLOR_FRAME_INT_CLR` writer - write 1 to clear color frame done"]
54pub type COLOR_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
55#[doc = "Field `YUV2RGB_FRAME_INT_CLR` writer - write 1 to clear yuv2rgb frame done"]
56pub type YUV2RGB_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `TAIL_IDI_FRAME_INT_CLR` writer - write 1 to clear isp_tail idi frame_end"]
58pub type TAIL_IDI_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
59#[doc = "Field `HEADER_IDI_FRAME_INT_CLR` writer - write 1 to clear real input frame end of isp_input"]
60pub type HEADER_IDI_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
63    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
64        write!(f, "(not readable)")
65    }
66}
67impl W {
68    #[doc = "Bit 0 - write 1 to clear input data type error"]
69    #[inline(always)]
70    #[must_use]
71    pub fn isp_data_type_err_int_clr(&mut self) -> ISP_DATA_TYPE_ERR_INT_CLR_W<INT_CLR_SPEC> {
72        ISP_DATA_TYPE_ERR_INT_CLR_W::new(self, 0)
73    }
74    #[doc = "Bit 1 - write 1 to clear isp input fifo overflow"]
75    #[inline(always)]
76    #[must_use]
77    pub fn isp_async_fifo_ovf_int_clr(&mut self) -> ISP_ASYNC_FIFO_OVF_INT_CLR_W<INT_CLR_SPEC> {
78        ISP_ASYNC_FIFO_OVF_INT_CLR_W::new(self, 1)
79    }
80    #[doc = "Bit 2 - write 1 to clear isp input buffer full"]
81    #[inline(always)]
82    #[must_use]
83    pub fn isp_buf_full_int_clr(&mut self) -> ISP_BUF_FULL_INT_CLR_W<INT_CLR_SPEC> {
84        ISP_BUF_FULL_INT_CLR_W::new(self, 2)
85    }
86    #[doc = "Bit 3 - write 1 to clear hnum and vnum setting format error"]
87    #[inline(always)]
88    #[must_use]
89    pub fn isp_hvnum_setting_err_int_clr(
90        &mut self,
91    ) -> ISP_HVNUM_SETTING_ERR_INT_CLR_W<INT_CLR_SPEC> {
92        ISP_HVNUM_SETTING_ERR_INT_CLR_W::new(self, 3)
93    }
94    #[doc = "Bit 4 - write 1 to clear setting invalid reg_data_type"]
95    #[inline(always)]
96    #[must_use]
97    pub fn isp_data_type_setting_err_int_clr(
98        &mut self,
99    ) -> ISP_DATA_TYPE_SETTING_ERR_INT_CLR_W<INT_CLR_SPEC> {
100        ISP_DATA_TYPE_SETTING_ERR_INT_CLR_W::new(self, 4)
101    }
102    #[doc = "Bit 5 - write 1 to clear hnum setting unmatch with mipi input"]
103    #[inline(always)]
104    #[must_use]
105    pub fn isp_mipi_hnum_unmatch_int_clr(
106        &mut self,
107    ) -> ISP_MIPI_HNUM_UNMATCH_INT_CLR_W<INT_CLR_SPEC> {
108        ISP_MIPI_HNUM_UNMATCH_INT_CLR_W::new(self, 5)
109    }
110    #[doc = "Bit 6 - write 1 to clear dpc check done"]
111    #[inline(always)]
112    #[must_use]
113    pub fn dpc_check_done_int_clr(&mut self) -> DPC_CHECK_DONE_INT_CLR_W<INT_CLR_SPEC> {
114        DPC_CHECK_DONE_INT_CLR_W::new(self, 6)
115    }
116    #[doc = "Bit 7 - write 1 to clear gamma setting error"]
117    #[inline(always)]
118    #[must_use]
119    pub fn gamma_xcoord_err_int_clr(&mut self) -> GAMMA_XCOORD_ERR_INT_CLR_W<INT_CLR_SPEC> {
120        GAMMA_XCOORD_ERR_INT_CLR_W::new(self, 7)
121    }
122    #[doc = "Bit 8 - write 1 to clear ae monitor"]
123    #[inline(always)]
124    #[must_use]
125    pub fn ae_monitor_int_clr(&mut self) -> AE_MONITOR_INT_CLR_W<INT_CLR_SPEC> {
126        AE_MONITOR_INT_CLR_W::new(self, 8)
127    }
128    #[doc = "Bit 9 - write 1 to clear ae"]
129    #[inline(always)]
130    #[must_use]
131    pub fn ae_frame_done_int_clr(&mut self) -> AE_FRAME_DONE_INT_CLR_W<INT_CLR_SPEC> {
132        AE_FRAME_DONE_INT_CLR_W::new(self, 9)
133    }
134    #[doc = "Bit 10 - write 1 to clear af statistic"]
135    #[inline(always)]
136    #[must_use]
137    pub fn af_fdone_int_clr(&mut self) -> AF_FDONE_INT_CLR_W<INT_CLR_SPEC> {
138        AF_FDONE_INT_CLR_W::new(self, 10)
139    }
140    #[doc = "Bit 11 - write 1 to clear af monitor"]
141    #[inline(always)]
142    #[must_use]
143    pub fn af_env_int_clr(&mut self) -> AF_ENV_INT_CLR_W<INT_CLR_SPEC> {
144        AF_ENV_INT_CLR_W::new(self, 11)
145    }
146    #[doc = "Bit 12 - write 1 to clear awb"]
147    #[inline(always)]
148    #[must_use]
149    pub fn awb_fdone_int_clr(&mut self) -> AWB_FDONE_INT_CLR_W<INT_CLR_SPEC> {
150        AWB_FDONE_INT_CLR_W::new(self, 12)
151    }
152    #[doc = "Bit 13 - write 1 to clear histogram"]
153    #[inline(always)]
154    #[must_use]
155    pub fn hist_fdone_int_clr(&mut self) -> HIST_FDONE_INT_CLR_W<INT_CLR_SPEC> {
156        HIST_FDONE_INT_CLR_W::new(self, 13)
157    }
158    #[doc = "Bit 14 - write 1 to clear isp frame end"]
159    #[inline(always)]
160    #[must_use]
161    pub fn frame_int_clr(&mut self) -> FRAME_INT_CLR_W<INT_CLR_SPEC> {
162        FRAME_INT_CLR_W::new(self, 14)
163    }
164    #[doc = "Bit 15 - write 1 to clear blc frame done"]
165    #[inline(always)]
166    #[must_use]
167    pub fn blc_frame_int_clr(&mut self) -> BLC_FRAME_INT_CLR_W<INT_CLR_SPEC> {
168        BLC_FRAME_INT_CLR_W::new(self, 15)
169    }
170    #[doc = "Bit 16 - write 1 to clear lsc frame done"]
171    #[inline(always)]
172    #[must_use]
173    pub fn lsc_frame_int_clr(&mut self) -> LSC_FRAME_INT_CLR_W<INT_CLR_SPEC> {
174        LSC_FRAME_INT_CLR_W::new(self, 16)
175    }
176    #[doc = "Bit 17 - write 1 to clear dpc frame done"]
177    #[inline(always)]
178    #[must_use]
179    pub fn dpc_frame_int_clr(&mut self) -> DPC_FRAME_INT_CLR_W<INT_CLR_SPEC> {
180        DPC_FRAME_INT_CLR_W::new(self, 17)
181    }
182    #[doc = "Bit 18 - write 1 to clear bf frame done"]
183    #[inline(always)]
184    #[must_use]
185    pub fn bf_frame_int_clr(&mut self) -> BF_FRAME_INT_CLR_W<INT_CLR_SPEC> {
186        BF_FRAME_INT_CLR_W::new(self, 18)
187    }
188    #[doc = "Bit 19 - write 1 to clear demosaic frame done"]
189    #[inline(always)]
190    #[must_use]
191    pub fn demosaic_frame_int_clr(&mut self) -> DEMOSAIC_FRAME_INT_CLR_W<INT_CLR_SPEC> {
192        DEMOSAIC_FRAME_INT_CLR_W::new(self, 19)
193    }
194    #[doc = "Bit 20 - write 1 to clear median frame done"]
195    #[inline(always)]
196    #[must_use]
197    pub fn median_frame_int_clr(&mut self) -> MEDIAN_FRAME_INT_CLR_W<INT_CLR_SPEC> {
198        MEDIAN_FRAME_INT_CLR_W::new(self, 20)
199    }
200    #[doc = "Bit 21 - write 1 to clear ccm frame done"]
201    #[inline(always)]
202    #[must_use]
203    pub fn ccm_frame_int_clr(&mut self) -> CCM_FRAME_INT_CLR_W<INT_CLR_SPEC> {
204        CCM_FRAME_INT_CLR_W::new(self, 21)
205    }
206    #[doc = "Bit 22 - write 1 to clear gamma frame done"]
207    #[inline(always)]
208    #[must_use]
209    pub fn gamma_frame_int_clr(&mut self) -> GAMMA_FRAME_INT_CLR_W<INT_CLR_SPEC> {
210        GAMMA_FRAME_INT_CLR_W::new(self, 22)
211    }
212    #[doc = "Bit 23 - write 1 to clear rgb2yuv frame done"]
213    #[inline(always)]
214    #[must_use]
215    pub fn rgb2yuv_frame_int_clr(&mut self) -> RGB2YUV_FRAME_INT_CLR_W<INT_CLR_SPEC> {
216        RGB2YUV_FRAME_INT_CLR_W::new(self, 23)
217    }
218    #[doc = "Bit 24 - write 1 to clear sharp frame done"]
219    #[inline(always)]
220    #[must_use]
221    pub fn sharp_frame_int_clr(&mut self) -> SHARP_FRAME_INT_CLR_W<INT_CLR_SPEC> {
222        SHARP_FRAME_INT_CLR_W::new(self, 24)
223    }
224    #[doc = "Bit 25 - write 1 to clear color frame done"]
225    #[inline(always)]
226    #[must_use]
227    pub fn color_frame_int_clr(&mut self) -> COLOR_FRAME_INT_CLR_W<INT_CLR_SPEC> {
228        COLOR_FRAME_INT_CLR_W::new(self, 25)
229    }
230    #[doc = "Bit 26 - write 1 to clear yuv2rgb frame done"]
231    #[inline(always)]
232    #[must_use]
233    pub fn yuv2rgb_frame_int_clr(&mut self) -> YUV2RGB_FRAME_INT_CLR_W<INT_CLR_SPEC> {
234        YUV2RGB_FRAME_INT_CLR_W::new(self, 26)
235    }
236    #[doc = "Bit 27 - write 1 to clear isp_tail idi frame_end"]
237    #[inline(always)]
238    #[must_use]
239    pub fn tail_idi_frame_int_clr(&mut self) -> TAIL_IDI_FRAME_INT_CLR_W<INT_CLR_SPEC> {
240        TAIL_IDI_FRAME_INT_CLR_W::new(self, 27)
241    }
242    #[doc = "Bit 28 - write 1 to clear real input frame end of isp_input"]
243    #[inline(always)]
244    #[must_use]
245    pub fn header_idi_frame_int_clr(&mut self) -> HEADER_IDI_FRAME_INT_CLR_W<INT_CLR_SPEC> {
246        HEADER_IDI_FRAME_INT_CLR_W::new(self, 28)
247    }
248}
249#[doc = "interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
250pub struct INT_CLR_SPEC;
251impl crate::RegisterSpec for INT_CLR_SPEC {
252    type Ux = u32;
253}
254#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
255impl crate::Writable for INT_CLR_SPEC {
256    type Safety = crate::Unsafe;
257    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
258    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
259}
260#[doc = "`reset()` method sets INT_CLR to value 0"]
261impl crate::Resettable for INT_CLR_SPEC {
262    const RESET_VALUE: u32 = 0;
263}
esp32p4/isp/int_clr.rs

esp32p4/isp/
int_clr.rs
