esp32p4/i3c_mst/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `TX_DATA_BUF_THLD_INT_CLR` writer - NA"]
4pub type TX_DATA_BUF_THLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `RX_DATA_BUF_THLD_INT_CLR` writer - NA"]
6pub type RX_DATA_BUF_THLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `IBI_STATUS_THLD_INT_CLR` writer - NA"]
8pub type IBI_STATUS_THLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CMD_BUF_EMPTY_THLD_INT_CLR` writer - NA"]
10pub type CMD_BUF_EMPTY_THLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `RESP_READY_INT_CLR` writer - NA"]
12pub type RESP_READY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `NXT_CMD_REQ_ERR_INT_CLR` writer - NA"]
14pub type NXT_CMD_REQ_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `TRANSFER_ERR_INT_CLR` writer - NA"]
16pub type TRANSFER_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TRANSFER_COMPLETE_INT_CLR` writer - NA"]
18pub type TRANSFER_COMPLETE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `COMMAND_DONE_INT_CLR` writer - NA"]
20pub type COMMAND_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DETECT_START_INT_CLR` writer - NA"]
22pub type DETECT_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `RESP_BUF_OVF_INT_CLR` writer - NA"]
24pub type RESP_BUF_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `IBI_DATA_BUF_OVF_INT_CLR` writer - NA"]
26pub type IBI_DATA_BUF_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `IBI_STATUS_BUF_OVF_INT_CLR` writer - NA"]
28pub type IBI_STATUS_BUF_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `IBI_HANDLE_DONE_INT_CLR` writer - NA"]
30pub type IBI_HANDLE_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `IBI_DETECT_INT_CLR` writer - NA"]
32pub type IBI_DETECT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CMD_CCC_MISMATCH_INT_CLR` writer - NA"]
34pub type CMD_CCC_MISMATCH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[cfg(feature = "impl-register-debug")]
36impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
37    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
38        write!(f, "(not readable)")
39    }
40}
41impl W {
42    #[doc = "Bit 0 - NA"]
43    #[inline(always)]
44    #[must_use]
45    pub fn tx_data_buf_thld_int_clr(&mut self) -> TX_DATA_BUF_THLD_INT_CLR_W<INT_CLR_SPEC> {
46        TX_DATA_BUF_THLD_INT_CLR_W::new(self, 0)
47    }
48    #[doc = "Bit 1 - NA"]
49    #[inline(always)]
50    #[must_use]
51    pub fn rx_data_buf_thld_int_clr(&mut self) -> RX_DATA_BUF_THLD_INT_CLR_W<INT_CLR_SPEC> {
52        RX_DATA_BUF_THLD_INT_CLR_W::new(self, 1)
53    }
54    #[doc = "Bit 2 - NA"]
55    #[inline(always)]
56    #[must_use]
57    pub fn ibi_status_thld_int_clr(&mut self) -> IBI_STATUS_THLD_INT_CLR_W<INT_CLR_SPEC> {
58        IBI_STATUS_THLD_INT_CLR_W::new(self, 2)
59    }
60    #[doc = "Bit 3 - NA"]
61    #[inline(always)]
62    #[must_use]
63    pub fn cmd_buf_empty_thld_int_clr(&mut self) -> CMD_BUF_EMPTY_THLD_INT_CLR_W<INT_CLR_SPEC> {
64        CMD_BUF_EMPTY_THLD_INT_CLR_W::new(self, 3)
65    }
66    #[doc = "Bit 4 - NA"]
67    #[inline(always)]
68    #[must_use]
69    pub fn resp_ready_int_clr(&mut self) -> RESP_READY_INT_CLR_W<INT_CLR_SPEC> {
70        RESP_READY_INT_CLR_W::new(self, 4)
71    }
72    #[doc = "Bit 5 - NA"]
73    #[inline(always)]
74    #[must_use]
75    pub fn nxt_cmd_req_err_int_clr(&mut self) -> NXT_CMD_REQ_ERR_INT_CLR_W<INT_CLR_SPEC> {
76        NXT_CMD_REQ_ERR_INT_CLR_W::new(self, 5)
77    }
78    #[doc = "Bit 6 - NA"]
79    #[inline(always)]
80    #[must_use]
81    pub fn transfer_err_int_clr(&mut self) -> TRANSFER_ERR_INT_CLR_W<INT_CLR_SPEC> {
82        TRANSFER_ERR_INT_CLR_W::new(self, 6)
83    }
84    #[doc = "Bit 7 - NA"]
85    #[inline(always)]
86    #[must_use]
87    pub fn transfer_complete_int_clr(&mut self) -> TRANSFER_COMPLETE_INT_CLR_W<INT_CLR_SPEC> {
88        TRANSFER_COMPLETE_INT_CLR_W::new(self, 7)
89    }
90    #[doc = "Bit 8 - NA"]
91    #[inline(always)]
92    #[must_use]
93    pub fn command_done_int_clr(&mut self) -> COMMAND_DONE_INT_CLR_W<INT_CLR_SPEC> {
94        COMMAND_DONE_INT_CLR_W::new(self, 8)
95    }
96    #[doc = "Bit 9 - NA"]
97    #[inline(always)]
98    #[must_use]
99    pub fn detect_start_int_clr(&mut self) -> DETECT_START_INT_CLR_W<INT_CLR_SPEC> {
100        DETECT_START_INT_CLR_W::new(self, 9)
101    }
102    #[doc = "Bit 10 - NA"]
103    #[inline(always)]
104    #[must_use]
105    pub fn resp_buf_ovf_int_clr(&mut self) -> RESP_BUF_OVF_INT_CLR_W<INT_CLR_SPEC> {
106        RESP_BUF_OVF_INT_CLR_W::new(self, 10)
107    }
108    #[doc = "Bit 11 - NA"]
109    #[inline(always)]
110    #[must_use]
111    pub fn ibi_data_buf_ovf_int_clr(&mut self) -> IBI_DATA_BUF_OVF_INT_CLR_W<INT_CLR_SPEC> {
112        IBI_DATA_BUF_OVF_INT_CLR_W::new(self, 11)
113    }
114    #[doc = "Bit 12 - NA"]
115    #[inline(always)]
116    #[must_use]
117    pub fn ibi_status_buf_ovf_int_clr(&mut self) -> IBI_STATUS_BUF_OVF_INT_CLR_W<INT_CLR_SPEC> {
118        IBI_STATUS_BUF_OVF_INT_CLR_W::new(self, 12)
119    }
120    #[doc = "Bit 13 - NA"]
121    #[inline(always)]
122    #[must_use]
123    pub fn ibi_handle_done_int_clr(&mut self) -> IBI_HANDLE_DONE_INT_CLR_W<INT_CLR_SPEC> {
124        IBI_HANDLE_DONE_INT_CLR_W::new(self, 13)
125    }
126    #[doc = "Bit 14 - NA"]
127    #[inline(always)]
128    #[must_use]
129    pub fn ibi_detect_int_clr(&mut self) -> IBI_DETECT_INT_CLR_W<INT_CLR_SPEC> {
130        IBI_DETECT_INT_CLR_W::new(self, 14)
131    }
132    #[doc = "Bit 15 - NA"]
133    #[inline(always)]
134    #[must_use]
135    pub fn cmd_ccc_mismatch_int_clr(&mut self) -> CMD_CCC_MISMATCH_INT_CLR_W<INT_CLR_SPEC> {
136        CMD_CCC_MISMATCH_INT_CLR_W::new(self, 15)
137    }
138}
139#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
140pub struct INT_CLR_SPEC;
141impl crate::RegisterSpec for INT_CLR_SPEC {
142    type Ux = u32;
143}
144#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
145impl crate::Writable for INT_CLR_SPEC {
146    type Safety = crate::Unsafe;
147    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
148    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
149}
150#[doc = "`reset()` method sets INT_CLR to value 0"]
151impl crate::Resettable for INT_CLR_SPEC {
152    const RESET_VALUE: u32 = 0;
153}
esp32p4/i3c_mst/int_clr.rs

esp32p4/i3c_mst/
int_clr.rs
