esp32p4/h264_dma/out_ch/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `OUT_DONE` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."]
4pub type OUT_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `OUT_EOF` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."]
6pub type OUT_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `OUT_DSCR_ERR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."]
8pub type OUT_DSCR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `OUT_TOTAL_EOF` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."]
10pub type OUT_TOTAL_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `OUTFIFO_OVF_L1` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."]
12pub type OUTFIFO_OVF_L1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `OUTFIFO_UDF_L1` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."]
14pub type OUTFIFO_UDF_L1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `OUTFIFO_OVF_L2` writer - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt."]
16pub type OUTFIFO_OVF_L2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `OUTFIFO_UDF_L2` writer - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt."]
18pub type OUTFIFO_UDF_L2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `OUT_DSCR_TASK_OVF` writer - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt."]
20pub type OUT_DSCR_TASK_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[cfg(feature = "impl-register-debug")]
22impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
23    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
24        write!(f, "(not readable)")
25    }
26}
27impl W {
28    #[doc = "Bit 0 - Set this bit to clear the OUT_DONE_CH_INT interrupt."]
29    #[inline(always)]
30    #[must_use]
31    pub fn out_done(&mut self) -> OUT_DONE_W<INT_CLR_SPEC> {
32        OUT_DONE_W::new(self, 0)
33    }
34    #[doc = "Bit 1 - Set this bit to clear the OUT_EOF_CH_INT interrupt."]
35    #[inline(always)]
36    #[must_use]
37    pub fn out_eof(&mut self) -> OUT_EOF_W<INT_CLR_SPEC> {
38        OUT_EOF_W::new(self, 1)
39    }
40    #[doc = "Bit 2 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."]
41    #[inline(always)]
42    #[must_use]
43    pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<INT_CLR_SPEC> {
44        OUT_DSCR_ERR_W::new(self, 2)
45    }
46    #[doc = "Bit 3 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."]
47    #[inline(always)]
48    #[must_use]
49    pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<INT_CLR_SPEC> {
50        OUT_TOTAL_EOF_W::new(self, 3)
51    }
52    #[doc = "Bit 4 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."]
53    #[inline(always)]
54    #[must_use]
55    pub fn outfifo_ovf_l1(&mut self) -> OUTFIFO_OVF_L1_W<INT_CLR_SPEC> {
56        OUTFIFO_OVF_L1_W::new(self, 4)
57    }
58    #[doc = "Bit 5 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."]
59    #[inline(always)]
60    #[must_use]
61    pub fn outfifo_udf_l1(&mut self) -> OUTFIFO_UDF_L1_W<INT_CLR_SPEC> {
62        OUTFIFO_UDF_L1_W::new(self, 5)
63    }
64    #[doc = "Bit 6 - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt."]
65    #[inline(always)]
66    #[must_use]
67    pub fn outfifo_ovf_l2(&mut self) -> OUTFIFO_OVF_L2_W<INT_CLR_SPEC> {
68        OUTFIFO_OVF_L2_W::new(self, 6)
69    }
70    #[doc = "Bit 7 - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt."]
71    #[inline(always)]
72    #[must_use]
73    pub fn outfifo_udf_l2(&mut self) -> OUTFIFO_UDF_L2_W<INT_CLR_SPEC> {
74        OUTFIFO_UDF_L2_W::new(self, 7)
75    }
76    #[doc = "Bit 8 - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt."]
77    #[inline(always)]
78    #[must_use]
79    pub fn out_dscr_task_ovf(&mut self) -> OUT_DSCR_TASK_OVF_W<INT_CLR_SPEC> {
80        OUT_DSCR_TASK_OVF_W::new(self, 8)
81    }
82}
83#[doc = "TX CHx interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
84pub struct INT_CLR_SPEC;
85impl crate::RegisterSpec for INT_CLR_SPEC {
86    type Ux = u32;
87}
88#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
89impl crate::Writable for INT_CLR_SPEC {
90    type Safety = crate::Unsafe;
91    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
92    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01ff;
93}
94#[doc = "`reset()` method sets INT_CLR to value 0"]
95impl crate::Resettable for INT_CLR_SPEC {
96    const RESET_VALUE: u32 = 0;
97}
esp32p4/h264_dma/out_ch/int_clr.rs

esp32p4/h264_dma/out_ch/
int_clr.rs
