esp32p4/h264_dma/in_ch5/
int_raw.rs

1#[doc = "Register `INT_RAW` reader"]
2pub type R = crate::R<INT_RAW_SPEC>;
3#[doc = "Register `INT_RAW` writer"]
4pub type W = crate::W<INT_RAW_SPEC>;
5#[doc = "Field `IN_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."]
6pub type IN_DONE_R = crate::BitReader;
7#[doc = "Field `IN_DONE` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."]
8pub type IN_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `IN_SUC_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."]
10pub type IN_SUC_EOF_R = crate::BitReader;
11#[doc = "Field `IN_SUC_EOF` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."]
12pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `INFIFO_OVF_L1` reader - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."]
14pub type INFIFO_OVF_L1_R = crate::BitReader;
15#[doc = "Field `INFIFO_OVF_L1` writer - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."]
16pub type INFIFO_OVF_L1_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `INFIFO_UDF_L1` reader - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."]
18pub type INFIFO_UDF_L1_R = crate::BitReader;
19#[doc = "Field `INFIFO_UDF_L1` writer - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."]
20pub type INFIFO_UDF_L1_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FETCH_MB_COL_CNT_OVF` reader - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."]
22pub type FETCH_MB_COL_CNT_OVF_R = crate::BitReader;
23#[doc = "Field `FETCH_MB_COL_CNT_OVF` writer - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."]
24pub type FETCH_MB_COL_CNT_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."]
27    #[inline(always)]
28    pub fn in_done(&self) -> IN_DONE_R {
29        IN_DONE_R::new((self.bits & 1) != 0)
30    }
31    #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."]
32    #[inline(always)]
33    pub fn in_suc_eof(&self) -> IN_SUC_EOF_R {
34        IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0)
35    }
36    #[doc = "Bit 2 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."]
37    #[inline(always)]
38    pub fn infifo_ovf_l1(&self) -> INFIFO_OVF_L1_R {
39        INFIFO_OVF_L1_R::new(((self.bits >> 2) & 1) != 0)
40    }
41    #[doc = "Bit 3 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."]
42    #[inline(always)]
43    pub fn infifo_udf_l1(&self) -> INFIFO_UDF_L1_R {
44        INFIFO_UDF_L1_R::new(((self.bits >> 3) & 1) != 0)
45    }
46    #[doc = "Bit 4 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."]
47    #[inline(always)]
48    pub fn fetch_mb_col_cnt_ovf(&self) -> FETCH_MB_COL_CNT_OVF_R {
49        FETCH_MB_COL_CNT_OVF_R::new(((self.bits >> 4) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("INT_RAW")
56            .field("in_done", &format_args!("{}", self.in_done().bit()))
57            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
58            .field(
59                "infifo_ovf_l1",
60                &format_args!("{}", self.infifo_ovf_l1().bit()),
61            )
62            .field(
63                "infifo_udf_l1",
64                &format_args!("{}", self.infifo_udf_l1().bit()),
65            )
66            .field(
67                "fetch_mb_col_cnt_ovf",
68                &format_args!("{}", self.fetch_mb_col_cnt_ovf().bit()),
69            )
70            .finish()
71    }
72}
73#[cfg(feature = "impl-register-debug")]
74impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
75    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
76        core::fmt::Debug::fmt(&self.read(), f)
77    }
78}
79impl W {
80    #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."]
81    #[inline(always)]
82    #[must_use]
83    pub fn in_done(&mut self) -> IN_DONE_W<INT_RAW_SPEC> {
84        IN_DONE_W::new(self, 0)
85    }
86    #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."]
87    #[inline(always)]
88    #[must_use]
89    pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<INT_RAW_SPEC> {
90        IN_SUC_EOF_W::new(self, 1)
91    }
92    #[doc = "Bit 2 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."]
93    #[inline(always)]
94    #[must_use]
95    pub fn infifo_ovf_l1(&mut self) -> INFIFO_OVF_L1_W<INT_RAW_SPEC> {
96        INFIFO_OVF_L1_W::new(self, 2)
97    }
98    #[doc = "Bit 3 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."]
99    #[inline(always)]
100    #[must_use]
101    pub fn infifo_udf_l1(&mut self) -> INFIFO_UDF_L1_W<INT_RAW_SPEC> {
102        INFIFO_UDF_L1_W::new(self, 3)
103    }
104    #[doc = "Bit 4 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."]
105    #[inline(always)]
106    #[must_use]
107    pub fn fetch_mb_col_cnt_ovf(&mut self) -> FETCH_MB_COL_CNT_OVF_W<INT_RAW_SPEC> {
108        FETCH_MB_COL_CNT_OVF_W::new(self, 4)
109    }
110}
111#[doc = "RX CH5 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
112pub struct INT_RAW_SPEC;
113impl crate::RegisterSpec for INT_RAW_SPEC {
114    type Ux = u32;
115}
116#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
117impl crate::Readable for INT_RAW_SPEC {}
118#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"]
119impl crate::Writable for INT_RAW_SPEC {
120    type Safety = crate::Unsafe;
121    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
122    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
123}
124#[doc = "`reset()` method sets INT_RAW to value 0"]
125impl crate::Resettable for INT_RAW_SPEC {
126    const RESET_VALUE: u32 = 0;
127}
esp32p4/h264_dma/in_ch5/int_raw.rs

esp32p4/h264_dma/in_ch5/
int_raw.rs
