esp32p4/h264_dma/in_ch/
fifo_status.rs

1#[doc = "Register `FIFO_STATUS` reader"]
2pub type R = crate::R<FIFO_STATUS_SPEC>;
3#[doc = "Field `INFIFO_FULL_L2` reader - Rx FIFO full signal for Rx channel."]
4pub type INFIFO_FULL_L2_R = crate::BitReader;
5#[doc = "Field `INFIFO_EMPTY_L2` reader - Rx FIFO empty signal for Rx channel."]
6pub type INFIFO_EMPTY_L2_R = crate::BitReader;
7#[doc = "Field `INFIFO_CNT_L2` reader - The register stores the byte number of the data in Rx FIFO for Rx channel."]
8pub type INFIFO_CNT_L2_R = crate::FieldReader;
9#[doc = "Field `INFIFO_FULL_L1` reader - Tx FIFO full signal for Tx channel 0."]
10pub type INFIFO_FULL_L1_R = crate::BitReader;
11#[doc = "Field `INFIFO_EMPTY_L1` reader - Tx FIFO empty signal for Tx channel 0."]
12pub type INFIFO_EMPTY_L1_R = crate::BitReader;
13#[doc = "Field `INFIFO_CNT_L1` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 0."]
14pub type INFIFO_CNT_L1_R = crate::FieldReader;
15#[doc = "Field `INFIFO_FULL_L3` reader - Tx FIFO full signal for Tx channel 0."]
16pub type INFIFO_FULL_L3_R = crate::BitReader;
17#[doc = "Field `INFIFO_EMPTY_L3` reader - Tx FIFO empty signal for Tx channel 0."]
18pub type INFIFO_EMPTY_L3_R = crate::BitReader;
19#[doc = "Field `INFIFO_CNT_L3` reader - The register stores the 8byte number of the data in Tx FIFO for Tx channel 0."]
20pub type INFIFO_CNT_L3_R = crate::FieldReader;
21impl R {
22    #[doc = "Bit 0 - Rx FIFO full signal for Rx channel."]
23    #[inline(always)]
24    pub fn infifo_full_l2(&self) -> INFIFO_FULL_L2_R {
25        INFIFO_FULL_L2_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - Rx FIFO empty signal for Rx channel."]
28    #[inline(always)]
29    pub fn infifo_empty_l2(&self) -> INFIFO_EMPTY_L2_R {
30        INFIFO_EMPTY_L2_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bits 2:5 - The register stores the byte number of the data in Rx FIFO for Rx channel."]
33    #[inline(always)]
34    pub fn infifo_cnt_l2(&self) -> INFIFO_CNT_L2_R {
35        INFIFO_CNT_L2_R::new(((self.bits >> 2) & 0x0f) as u8)
36    }
37    #[doc = "Bit 6 - Tx FIFO full signal for Tx channel 0."]
38    #[inline(always)]
39    pub fn infifo_full_l1(&self) -> INFIFO_FULL_L1_R {
40        INFIFO_FULL_L1_R::new(((self.bits >> 6) & 1) != 0)
41    }
42    #[doc = "Bit 7 - Tx FIFO empty signal for Tx channel 0."]
43    #[inline(always)]
44    pub fn infifo_empty_l1(&self) -> INFIFO_EMPTY_L1_R {
45        INFIFO_EMPTY_L1_R::new(((self.bits >> 7) & 1) != 0)
46    }
47    #[doc = "Bits 8:12 - The register stores the byte number of the data in Tx FIFO for Tx channel 0."]
48    #[inline(always)]
49    pub fn infifo_cnt_l1(&self) -> INFIFO_CNT_L1_R {
50        INFIFO_CNT_L1_R::new(((self.bits >> 8) & 0x1f) as u8)
51    }
52    #[doc = "Bit 16 - Tx FIFO full signal for Tx channel 0."]
53    #[inline(always)]
54    pub fn infifo_full_l3(&self) -> INFIFO_FULL_L3_R {
55        INFIFO_FULL_L3_R::new(((self.bits >> 16) & 1) != 0)
56    }
57    #[doc = "Bit 17 - Tx FIFO empty signal for Tx channel 0."]
58    #[inline(always)]
59    pub fn infifo_empty_l3(&self) -> INFIFO_EMPTY_L3_R {
60        INFIFO_EMPTY_L3_R::new(((self.bits >> 17) & 1) != 0)
61    }
62    #[doc = "Bits 18:19 - The register stores the 8byte number of the data in Tx FIFO for Tx channel 0."]
63    #[inline(always)]
64    pub fn infifo_cnt_l3(&self) -> INFIFO_CNT_L3_R {
65        INFIFO_CNT_L3_R::new(((self.bits >> 18) & 3) as u8)
66    }
67}
68#[cfg(feature = "impl-register-debug")]
69impl core::fmt::Debug for R {
70    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
71        f.debug_struct("FIFO_STATUS")
72            .field(
73                "infifo_full_l2",
74                &format_args!("{}", self.infifo_full_l2().bit()),
75            )
76            .field(
77                "infifo_empty_l2",
78                &format_args!("{}", self.infifo_empty_l2().bit()),
79            )
80            .field(
81                "infifo_cnt_l2",
82                &format_args!("{}", self.infifo_cnt_l2().bits()),
83            )
84            .field(
85                "infifo_full_l1",
86                &format_args!("{}", self.infifo_full_l1().bit()),
87            )
88            .field(
89                "infifo_empty_l1",
90                &format_args!("{}", self.infifo_empty_l1().bit()),
91            )
92            .field(
93                "infifo_cnt_l1",
94                &format_args!("{}", self.infifo_cnt_l1().bits()),
95            )
96            .field(
97                "infifo_full_l3",
98                &format_args!("{}", self.infifo_full_l3().bit()),
99            )
100            .field(
101                "infifo_empty_l3",
102                &format_args!("{}", self.infifo_empty_l3().bit()),
103            )
104            .field(
105                "infifo_cnt_l3",
106                &format_args!("{}", self.infifo_cnt_l3().bits()),
107            )
108            .finish()
109    }
110}
111#[cfg(feature = "impl-register-debug")]
112impl core::fmt::Debug for crate::generic::Reg<FIFO_STATUS_SPEC> {
113    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
114        core::fmt::Debug::fmt(&self.read(), f)
115    }
116}
117#[doc = "RX CHx INFIFO status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
118pub struct FIFO_STATUS_SPEC;
119impl crate::RegisterSpec for FIFO_STATUS_SPEC {
120    type Ux = u32;
121}
122#[doc = "`read()` method returns [`fifo_status::R`](R) reader structure"]
123impl crate::Readable for FIFO_STATUS_SPEC {}
124#[doc = "`reset()` method sets FIFO_STATUS to value 0x0002_0082"]
125impl crate::Resettable for FIFO_STATUS_SPEC {
126    const RESET_VALUE: u32 = 0x0002_0082;
127}
esp32p4/h264_dma/in_ch/fifo_status.rs

esp32p4/h264_dma/in_ch/
fifo_status.rs
