esp32p4/cache/
l2_cache_data_mem_power_ctrl.rs

1#[doc = "Register `L2_CACHE_DATA_MEM_POWER_CTRL` reader"]
2pub type R = crate::R<L2_CACHE_DATA_MEM_POWER_CTRL_SPEC>;
3#[doc = "Register `L2_CACHE_DATA_MEM_POWER_CTRL` writer"]
4pub type W = crate::W<L2_CACHE_DATA_MEM_POWER_CTRL_SPEC>;
5#[doc = "Field `L2_CACHE_DATA_MEM_FORCE_ON` reader - The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating."]
6pub type L2_CACHE_DATA_MEM_FORCE_ON_R = crate::BitReader;
7#[doc = "Field `L2_CACHE_DATA_MEM_FORCE_ON` writer - The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating."]
8pub type L2_CACHE_DATA_MEM_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `L2_CACHE_DATA_MEM_FORCE_PD` reader - The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down"]
10pub type L2_CACHE_DATA_MEM_FORCE_PD_R = crate::BitReader;
11#[doc = "Field `L2_CACHE_DATA_MEM_FORCE_PD` writer - The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down"]
12pub type L2_CACHE_DATA_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `L2_CACHE_DATA_MEM_FORCE_PU` reader - The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up"]
14pub type L2_CACHE_DATA_MEM_FORCE_PU_R = crate::BitReader;
15#[doc = "Field `L2_CACHE_DATA_MEM_FORCE_PU` writer - The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up"]
16pub type L2_CACHE_DATA_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 20 - The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating."]
19    #[inline(always)]
20    pub fn l2_cache_data_mem_force_on(&self) -> L2_CACHE_DATA_MEM_FORCE_ON_R {
21        L2_CACHE_DATA_MEM_FORCE_ON_R::new(((self.bits >> 20) & 1) != 0)
22    }
23    #[doc = "Bit 21 - The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down"]
24    #[inline(always)]
25    pub fn l2_cache_data_mem_force_pd(&self) -> L2_CACHE_DATA_MEM_FORCE_PD_R {
26        L2_CACHE_DATA_MEM_FORCE_PD_R::new(((self.bits >> 21) & 1) != 0)
27    }
28    #[doc = "Bit 22 - The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up"]
29    #[inline(always)]
30    pub fn l2_cache_data_mem_force_pu(&self) -> L2_CACHE_DATA_MEM_FORCE_PU_R {
31        L2_CACHE_DATA_MEM_FORCE_PU_R::new(((self.bits >> 22) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("L2_CACHE_DATA_MEM_POWER_CTRL")
38            .field(
39                "l2_cache_data_mem_force_on",
40                &format_args!("{}", self.l2_cache_data_mem_force_on().bit()),
41            )
42            .field(
43                "l2_cache_data_mem_force_pd",
44                &format_args!("{}", self.l2_cache_data_mem_force_pd().bit()),
45            )
46            .field(
47                "l2_cache_data_mem_force_pu",
48                &format_args!("{}", self.l2_cache_data_mem_force_pu().bit()),
49            )
50            .finish()
51    }
52}
53#[cfg(feature = "impl-register-debug")]
54impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_DATA_MEM_POWER_CTRL_SPEC> {
55    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
56        core::fmt::Debug::fmt(&self.read(), f)
57    }
58}
59impl W {
60    #[doc = "Bit 20 - The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating."]
61    #[inline(always)]
62    #[must_use]
63    pub fn l2_cache_data_mem_force_on(
64        &mut self,
65    ) -> L2_CACHE_DATA_MEM_FORCE_ON_W<L2_CACHE_DATA_MEM_POWER_CTRL_SPEC> {
66        L2_CACHE_DATA_MEM_FORCE_ON_W::new(self, 20)
67    }
68    #[doc = "Bit 21 - The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down"]
69    #[inline(always)]
70    #[must_use]
71    pub fn l2_cache_data_mem_force_pd(
72        &mut self,
73    ) -> L2_CACHE_DATA_MEM_FORCE_PD_W<L2_CACHE_DATA_MEM_POWER_CTRL_SPEC> {
74        L2_CACHE_DATA_MEM_FORCE_PD_W::new(self, 21)
75    }
76    #[doc = "Bit 22 - The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up"]
77    #[inline(always)]
78    #[must_use]
79    pub fn l2_cache_data_mem_force_pu(
80        &mut self,
81    ) -> L2_CACHE_DATA_MEM_FORCE_PU_W<L2_CACHE_DATA_MEM_POWER_CTRL_SPEC> {
82        L2_CACHE_DATA_MEM_FORCE_PU_W::new(self, 22)
83    }
84}
85#[doc = "Cache data memory power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_data_mem_power_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_data_mem_power_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
86pub struct L2_CACHE_DATA_MEM_POWER_CTRL_SPEC;
87impl crate::RegisterSpec for L2_CACHE_DATA_MEM_POWER_CTRL_SPEC {
88    type Ux = u32;
89}
90#[doc = "`read()` method returns [`l2_cache_data_mem_power_ctrl::R`](R) reader structure"]
91impl crate::Readable for L2_CACHE_DATA_MEM_POWER_CTRL_SPEC {}
92#[doc = "`write(|w| ..)` method takes [`l2_cache_data_mem_power_ctrl::W`](W) writer structure"]
93impl crate::Writable for L2_CACHE_DATA_MEM_POWER_CTRL_SPEC {
94    type Safety = crate::Unsafe;
95    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
96    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
97}
98#[doc = "`reset()` method sets L2_CACHE_DATA_MEM_POWER_CTRL to value 0x0050_0000"]
99impl crate::Resettable for L2_CACHE_DATA_MEM_POWER_CTRL_SPEC {
100    const RESET_VALUE: u32 = 0x0050_0000;
101}
esp32p4/cache/l2_cache_data_mem_power_ctrl.rs

esp32p4/cache/
l2_cache_data_mem_power_ctrl.rs
