esp32p4/cache/
l2_bypass_cache_conf.rs

1#[doc = "Register `L2_BYPASS_CACHE_CONF` reader"]
2pub type R = crate::R<L2_BYPASS_CACHE_CONF_SPEC>;
3#[doc = "Register `L2_BYPASS_CACHE_CONF` writer"]
4pub type W = crate::W<L2_BYPASS_CACHE_CONF_SPEC>;
5#[doc = "Field `BYPASS_L2_CACHE_EN` reader - The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass."]
6pub type BYPASS_L2_CACHE_EN_R = crate::BitReader;
7#[doc = "Field `BYPASS_L2_CACHE_EN` writer - The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass."]
8pub type BYPASS_L2_CACHE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9impl R {
10    #[doc = "Bit 5 - The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass."]
11    #[inline(always)]
12    pub fn bypass_l2_cache_en(&self) -> BYPASS_L2_CACHE_EN_R {
13        BYPASS_L2_CACHE_EN_R::new(((self.bits >> 5) & 1) != 0)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("L2_BYPASS_CACHE_CONF")
20            .field(
21                "bypass_l2_cache_en",
22                &format_args!("{}", self.bypass_l2_cache_en().bit()),
23            )
24            .finish()
25    }
26}
27#[cfg(feature = "impl-register-debug")]
28impl core::fmt::Debug for crate::generic::Reg<L2_BYPASS_CACHE_CONF_SPEC> {
29    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
30        core::fmt::Debug::fmt(&self.read(), f)
31    }
32}
33impl W {
34    #[doc = "Bit 5 - The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass."]
35    #[inline(always)]
36    #[must_use]
37    pub fn bypass_l2_cache_en(&mut self) -> BYPASS_L2_CACHE_EN_W<L2_BYPASS_CACHE_CONF_SPEC> {
38        BYPASS_L2_CACHE_EN_W::new(self, 5)
39    }
40}
41#[doc = "Bypass Cache configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_bypass_cache_conf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_bypass_cache_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
42pub struct L2_BYPASS_CACHE_CONF_SPEC;
43impl crate::RegisterSpec for L2_BYPASS_CACHE_CONF_SPEC {
44    type Ux = u32;
45}
46#[doc = "`read()` method returns [`l2_bypass_cache_conf::R`](R) reader structure"]
47impl crate::Readable for L2_BYPASS_CACHE_CONF_SPEC {}
48#[doc = "`write(|w| ..)` method takes [`l2_bypass_cache_conf::W`](W) writer structure"]
49impl crate::Writable for L2_BYPASS_CACHE_CONF_SPEC {
50    type Safety = crate::Unsafe;
51    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
52    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
53}
54#[doc = "`reset()` method sets L2_BYPASS_CACHE_CONF to value 0"]
55impl crate::Resettable for L2_BYPASS_CACHE_CONF_SPEC {
56    const RESET_VALUE: u32 = 0;
57}
esp32p4/cache/l2_bypass_cache_conf.rs

esp32p4/cache/
l2_bypass_cache_conf.rs
