esp32p4/cache/
l1_icache_cachesize_conf.rs1#[doc = "Register `L1_ICACHE_CACHESIZE_CONF` reader"]
2pub type R = crate::R<L1_ICACHE_CACHESIZE_CONF_SPEC>;
3#[doc = "Field `L1_ICACHE_CACHESIZE_256` reader - The field is used to configure cachesize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot."]
4pub type L1_ICACHE_CACHESIZE_256_R = crate::BitReader;
5#[doc = "Field `L1_ICACHE_CACHESIZE_512` reader - The field is used to configure cachesize of L1-ICache as 512 bytes. This field and all other fields within this register is onehot."]
6pub type L1_ICACHE_CACHESIZE_512_R = crate::BitReader;
7#[doc = "Field `L1_ICACHE_CACHESIZE_1K` reader - The field is used to configure cachesize of L1-ICache as 1k bytes. This field and all other fields within this register is onehot."]
8pub type L1_ICACHE_CACHESIZE_1K_R = crate::BitReader;
9#[doc = "Field `L1_ICACHE_CACHESIZE_2K` reader - The field is used to configure cachesize of L1-ICache as 2k bytes. This field and all other fields within this register is onehot."]
10pub type L1_ICACHE_CACHESIZE_2K_R = crate::BitReader;
11#[doc = "Field `L1_ICACHE_CACHESIZE_4K` reader - The field is used to configure cachesize of L1-ICache as 4k bytes. This field and all other fields within this register is onehot."]
12pub type L1_ICACHE_CACHESIZE_4K_R = crate::BitReader;
13#[doc = "Field `L1_ICACHE_CACHESIZE_8K` reader - The field is used to configure cachesize of L1-ICache as 8k bytes. This field and all other fields within this register is onehot."]
14pub type L1_ICACHE_CACHESIZE_8K_R = crate::BitReader;
15#[doc = "Field `L1_ICACHE_CACHESIZE_16K` reader - The field is used to configure cachesize of L1-ICache as 16k bytes. This field and all other fields within this register is onehot."]
16pub type L1_ICACHE_CACHESIZE_16K_R = crate::BitReader;
17#[doc = "Field `L1_ICACHE_CACHESIZE_32K` reader - The field is used to configure cachesize of L1-ICache as 32k bytes. This field and all other fields within this register is onehot."]
18pub type L1_ICACHE_CACHESIZE_32K_R = crate::BitReader;
19#[doc = "Field `L1_ICACHE_CACHESIZE_64K` reader - The field is used to configure cachesize of L1-ICache as 64k bytes. This field and all other fields within this register is onehot."]
20pub type L1_ICACHE_CACHESIZE_64K_R = crate::BitReader;
21#[doc = "Field `L1_ICACHE_CACHESIZE_128K` reader - The field is used to configure cachesize of L1-ICache as 128k bytes. This field and all other fields within this register is onehot."]
22pub type L1_ICACHE_CACHESIZE_128K_R = crate::BitReader;
23#[doc = "Field `L1_ICACHE_CACHESIZE_256K` reader - The field is used to configure cachesize of L1-ICache as 256k bytes. This field and all other fields within this register is onehot."]
24pub type L1_ICACHE_CACHESIZE_256K_R = crate::BitReader;
25#[doc = "Field `L1_ICACHE_CACHESIZE_512K` reader - The field is used to configure cachesize of L1-ICache as 512k bytes. This field and all other fields within this register is onehot."]
26pub type L1_ICACHE_CACHESIZE_512K_R = crate::BitReader;
27#[doc = "Field `L1_ICACHE_CACHESIZE_1024K` reader - The field is used to configure cachesize of L1-ICache as 1024k bytes. This field and all other fields within this register is onehot."]
28pub type L1_ICACHE_CACHESIZE_1024K_R = crate::BitReader;
29impl R {
30 #[doc = "Bit 0 - The field is used to configure cachesize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot."]
31 #[inline(always)]
32 pub fn l1_icache_cachesize_256(&self) -> L1_ICACHE_CACHESIZE_256_R {
33 L1_ICACHE_CACHESIZE_256_R::new((self.bits & 1) != 0)
34 }
35 #[doc = "Bit 1 - The field is used to configure cachesize of L1-ICache as 512 bytes. This field and all other fields within this register is onehot."]
36 #[inline(always)]
37 pub fn l1_icache_cachesize_512(&self) -> L1_ICACHE_CACHESIZE_512_R {
38 L1_ICACHE_CACHESIZE_512_R::new(((self.bits >> 1) & 1) != 0)
39 }
40 #[doc = "Bit 2 - The field is used to configure cachesize of L1-ICache as 1k bytes. This field and all other fields within this register is onehot."]
41 #[inline(always)]
42 pub fn l1_icache_cachesize_1k(&self) -> L1_ICACHE_CACHESIZE_1K_R {
43 L1_ICACHE_CACHESIZE_1K_R::new(((self.bits >> 2) & 1) != 0)
44 }
45 #[doc = "Bit 3 - The field is used to configure cachesize of L1-ICache as 2k bytes. This field and all other fields within this register is onehot."]
46 #[inline(always)]
47 pub fn l1_icache_cachesize_2k(&self) -> L1_ICACHE_CACHESIZE_2K_R {
48 L1_ICACHE_CACHESIZE_2K_R::new(((self.bits >> 3) & 1) != 0)
49 }
50 #[doc = "Bit 4 - The field is used to configure cachesize of L1-ICache as 4k bytes. This field and all other fields within this register is onehot."]
51 #[inline(always)]
52 pub fn l1_icache_cachesize_4k(&self) -> L1_ICACHE_CACHESIZE_4K_R {
53 L1_ICACHE_CACHESIZE_4K_R::new(((self.bits >> 4) & 1) != 0)
54 }
55 #[doc = "Bit 5 - The field is used to configure cachesize of L1-ICache as 8k bytes. This field and all other fields within this register is onehot."]
56 #[inline(always)]
57 pub fn l1_icache_cachesize_8k(&self) -> L1_ICACHE_CACHESIZE_8K_R {
58 L1_ICACHE_CACHESIZE_8K_R::new(((self.bits >> 5) & 1) != 0)
59 }
60 #[doc = "Bit 6 - The field is used to configure cachesize of L1-ICache as 16k bytes. This field and all other fields within this register is onehot."]
61 #[inline(always)]
62 pub fn l1_icache_cachesize_16k(&self) -> L1_ICACHE_CACHESIZE_16K_R {
63 L1_ICACHE_CACHESIZE_16K_R::new(((self.bits >> 6) & 1) != 0)
64 }
65 #[doc = "Bit 7 - The field is used to configure cachesize of L1-ICache as 32k bytes. This field and all other fields within this register is onehot."]
66 #[inline(always)]
67 pub fn l1_icache_cachesize_32k(&self) -> L1_ICACHE_CACHESIZE_32K_R {
68 L1_ICACHE_CACHESIZE_32K_R::new(((self.bits >> 7) & 1) != 0)
69 }
70 #[doc = "Bit 8 - The field is used to configure cachesize of L1-ICache as 64k bytes. This field and all other fields within this register is onehot."]
71 #[inline(always)]
72 pub fn l1_icache_cachesize_64k(&self) -> L1_ICACHE_CACHESIZE_64K_R {
73 L1_ICACHE_CACHESIZE_64K_R::new(((self.bits >> 8) & 1) != 0)
74 }
75 #[doc = "Bit 9 - The field is used to configure cachesize of L1-ICache as 128k bytes. This field and all other fields within this register is onehot."]
76 #[inline(always)]
77 pub fn l1_icache_cachesize_128k(&self) -> L1_ICACHE_CACHESIZE_128K_R {
78 L1_ICACHE_CACHESIZE_128K_R::new(((self.bits >> 9) & 1) != 0)
79 }
80 #[doc = "Bit 10 - The field is used to configure cachesize of L1-ICache as 256k bytes. This field and all other fields within this register is onehot."]
81 #[inline(always)]
82 pub fn l1_icache_cachesize_256k(&self) -> L1_ICACHE_CACHESIZE_256K_R {
83 L1_ICACHE_CACHESIZE_256K_R::new(((self.bits >> 10) & 1) != 0)
84 }
85 #[doc = "Bit 11 - The field is used to configure cachesize of L1-ICache as 512k bytes. This field and all other fields within this register is onehot."]
86 #[inline(always)]
87 pub fn l1_icache_cachesize_512k(&self) -> L1_ICACHE_CACHESIZE_512K_R {
88 L1_ICACHE_CACHESIZE_512K_R::new(((self.bits >> 11) & 1) != 0)
89 }
90 #[doc = "Bit 12 - The field is used to configure cachesize of L1-ICache as 1024k bytes. This field and all other fields within this register is onehot."]
91 #[inline(always)]
92 pub fn l1_icache_cachesize_1024k(&self) -> L1_ICACHE_CACHESIZE_1024K_R {
93 L1_ICACHE_CACHESIZE_1024K_R::new(((self.bits >> 12) & 1) != 0)
94 }
95}
96#[cfg(feature = "impl-register-debug")]
97impl core::fmt::Debug for R {
98 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
99 f.debug_struct("L1_ICACHE_CACHESIZE_CONF")
100 .field(
101 "l1_icache_cachesize_256",
102 &format_args!("{}", self.l1_icache_cachesize_256().bit()),
103 )
104 .field(
105 "l1_icache_cachesize_512",
106 &format_args!("{}", self.l1_icache_cachesize_512().bit()),
107 )
108 .field(
109 "l1_icache_cachesize_1k",
110 &format_args!("{}", self.l1_icache_cachesize_1k().bit()),
111 )
112 .field(
113 "l1_icache_cachesize_2k",
114 &format_args!("{}", self.l1_icache_cachesize_2k().bit()),
115 )
116 .field(
117 "l1_icache_cachesize_4k",
118 &format_args!("{}", self.l1_icache_cachesize_4k().bit()),
119 )
120 .field(
121 "l1_icache_cachesize_8k",
122 &format_args!("{}", self.l1_icache_cachesize_8k().bit()),
123 )
124 .field(
125 "l1_icache_cachesize_16k",
126 &format_args!("{}", self.l1_icache_cachesize_16k().bit()),
127 )
128 .field(
129 "l1_icache_cachesize_32k",
130 &format_args!("{}", self.l1_icache_cachesize_32k().bit()),
131 )
132 .field(
133 "l1_icache_cachesize_64k",
134 &format_args!("{}", self.l1_icache_cachesize_64k().bit()),
135 )
136 .field(
137 "l1_icache_cachesize_128k",
138 &format_args!("{}", self.l1_icache_cachesize_128k().bit()),
139 )
140 .field(
141 "l1_icache_cachesize_256k",
142 &format_args!("{}", self.l1_icache_cachesize_256k().bit()),
143 )
144 .field(
145 "l1_icache_cachesize_512k",
146 &format_args!("{}", self.l1_icache_cachesize_512k().bit()),
147 )
148 .field(
149 "l1_icache_cachesize_1024k",
150 &format_args!("{}", self.l1_icache_cachesize_1024k().bit()),
151 )
152 .finish()
153 }
154}
155#[cfg(feature = "impl-register-debug")]
156impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE_CACHESIZE_CONF_SPEC> {
157 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
158 core::fmt::Debug::fmt(&self.read(), f)
159 }
160}
161#[doc = "L1 instruction Cache CacheSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache_cachesize_conf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
162pub struct L1_ICACHE_CACHESIZE_CONF_SPEC;
163impl crate::RegisterSpec for L1_ICACHE_CACHESIZE_CONF_SPEC {
164 type Ux = u32;
165}
166#[doc = "`read()` method returns [`l1_icache_cachesize_conf::R`](R) reader structure"]
167impl crate::Readable for L1_ICACHE_CACHESIZE_CONF_SPEC {}
168#[doc = "`reset()` method sets L1_ICACHE_CACHESIZE_CONF to value 0x40"]
169impl crate::Resettable for L1_ICACHE_CACHESIZE_CONF_SPEC {
170 const RESET_VALUE: u32 = 0x40;
171}