esp32p4/cache/
l1_dcache_preload_ctrl.rs

1#[doc = "Register `L1_DCACHE_PRELOAD_CTRL` reader"]
2pub type R = crate::R<L1_DCACHE_PRELOAD_CTRL_SPEC>;
3#[doc = "Register `L1_DCACHE_PRELOAD_CTRL` writer"]
4pub type W = crate::W<L1_DCACHE_PRELOAD_CTRL_SPEC>;
5#[doc = "Field `L1_DCACHE_PRELOAD_ENA` reader - The bit is used to enable preload operation on L1-DCache. It will be cleared by hardware automatically after preload operation is done."]
6pub type L1_DCACHE_PRELOAD_ENA_R = crate::BitReader;
7#[doc = "Field `L1_DCACHE_PRELOAD_ENA` writer - The bit is used to enable preload operation on L1-DCache. It will be cleared by hardware automatically after preload operation is done."]
8pub type L1_DCACHE_PRELOAD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `L1_DCACHE_PRELOAD_DONE` reader - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished."]
10pub type L1_DCACHE_PRELOAD_DONE_R = crate::BitReader;
11#[doc = "Field `L1_DCACHE_PRELOAD_ORDER` reader - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."]
12pub type L1_DCACHE_PRELOAD_ORDER_R = crate::BitReader;
13#[doc = "Field `L1_DCACHE_PRELOAD_ORDER` writer - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."]
14pub type L1_DCACHE_PRELOAD_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `L1_DCACHE_PRELOAD_RGID` reader - The bit is used to set the gid of l1 dcache preload."]
16pub type L1_DCACHE_PRELOAD_RGID_R = crate::FieldReader;
17#[doc = "Field `L1_DCACHE_PRELOAD_RGID` writer - The bit is used to set the gid of l1 dcache preload."]
18pub type L1_DCACHE_PRELOAD_RGID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
19impl R {
20    #[doc = "Bit 0 - The bit is used to enable preload operation on L1-DCache. It will be cleared by hardware automatically after preload operation is done."]
21    #[inline(always)]
22    pub fn l1_dcache_preload_ena(&self) -> L1_DCACHE_PRELOAD_ENA_R {
23        L1_DCACHE_PRELOAD_ENA_R::new((self.bits & 1) != 0)
24    }
25    #[doc = "Bit 1 - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished."]
26    #[inline(always)]
27    pub fn l1_dcache_preload_done(&self) -> L1_DCACHE_PRELOAD_DONE_R {
28        L1_DCACHE_PRELOAD_DONE_R::new(((self.bits >> 1) & 1) != 0)
29    }
30    #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."]
31    #[inline(always)]
32    pub fn l1_dcache_preload_order(&self) -> L1_DCACHE_PRELOAD_ORDER_R {
33        L1_DCACHE_PRELOAD_ORDER_R::new(((self.bits >> 2) & 1) != 0)
34    }
35    #[doc = "Bits 3:6 - The bit is used to set the gid of l1 dcache preload."]
36    #[inline(always)]
37    pub fn l1_dcache_preload_rgid(&self) -> L1_DCACHE_PRELOAD_RGID_R {
38        L1_DCACHE_PRELOAD_RGID_R::new(((self.bits >> 3) & 0x0f) as u8)
39    }
40}
41#[cfg(feature = "impl-register-debug")]
42impl core::fmt::Debug for R {
43    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
44        f.debug_struct("L1_DCACHE_PRELOAD_CTRL")
45            .field(
46                "l1_dcache_preload_ena",
47                &format_args!("{}", self.l1_dcache_preload_ena().bit()),
48            )
49            .field(
50                "l1_dcache_preload_done",
51                &format_args!("{}", self.l1_dcache_preload_done().bit()),
52            )
53            .field(
54                "l1_dcache_preload_order",
55                &format_args!("{}", self.l1_dcache_preload_order().bit()),
56            )
57            .field(
58                "l1_dcache_preload_rgid",
59                &format_args!("{}", self.l1_dcache_preload_rgid().bits()),
60            )
61            .finish()
62    }
63}
64#[cfg(feature = "impl-register-debug")]
65impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_PRELOAD_CTRL_SPEC> {
66    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
67        core::fmt::Debug::fmt(&self.read(), f)
68    }
69}
70impl W {
71    #[doc = "Bit 0 - The bit is used to enable preload operation on L1-DCache. It will be cleared by hardware automatically after preload operation is done."]
72    #[inline(always)]
73    #[must_use]
74    pub fn l1_dcache_preload_ena(
75        &mut self,
76    ) -> L1_DCACHE_PRELOAD_ENA_W<L1_DCACHE_PRELOAD_CTRL_SPEC> {
77        L1_DCACHE_PRELOAD_ENA_W::new(self, 0)
78    }
79    #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."]
80    #[inline(always)]
81    #[must_use]
82    pub fn l1_dcache_preload_order(
83        &mut self,
84    ) -> L1_DCACHE_PRELOAD_ORDER_W<L1_DCACHE_PRELOAD_CTRL_SPEC> {
85        L1_DCACHE_PRELOAD_ORDER_W::new(self, 2)
86    }
87    #[doc = "Bits 3:6 - The bit is used to set the gid of l1 dcache preload."]
88    #[inline(always)]
89    #[must_use]
90    pub fn l1_dcache_preload_rgid(
91        &mut self,
92    ) -> L1_DCACHE_PRELOAD_RGID_W<L1_DCACHE_PRELOAD_CTRL_SPEC> {
93        L1_DCACHE_PRELOAD_RGID_W::new(self, 3)
94    }
95}
96#[doc = "L1 data Cache preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_preload_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_preload_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
97pub struct L1_DCACHE_PRELOAD_CTRL_SPEC;
98impl crate::RegisterSpec for L1_DCACHE_PRELOAD_CTRL_SPEC {
99    type Ux = u32;
100}
101#[doc = "`read()` method returns [`l1_dcache_preload_ctrl::R`](R) reader structure"]
102impl crate::Readable for L1_DCACHE_PRELOAD_CTRL_SPEC {}
103#[doc = "`write(|w| ..)` method takes [`l1_dcache_preload_ctrl::W`](W) writer structure"]
104impl crate::Writable for L1_DCACHE_PRELOAD_CTRL_SPEC {
105    type Safety = crate::Unsafe;
106    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
107    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
108}
109#[doc = "`reset()` method sets L1_DCACHE_PRELOAD_CTRL to value 0x02"]
110impl crate::Resettable for L1_DCACHE_PRELOAD_CTRL_SPEC {
111    const RESET_VALUE: u32 = 0x02;
112}
esp32p4/cache/l1_dcache_preload_ctrl.rs

esp32p4/cache/
l1_dcache_preload_ctrl.rs
