esp32p4/cache/
l1_cache_object_ctrl.rs1#[doc = "Register `L1_CACHE_OBJECT_CTRL` reader"]
2pub type R = crate::R<L1_CACHE_OBJECT_CTRL_SPEC>;
3#[doc = "Register `L1_CACHE_OBJECT_CTRL` writer"]
4pub type W = crate::W<L1_CACHE_OBJECT_CTRL_SPEC>;
5#[doc = "Field `L1_ICACHE0_TAG_OBJECT` reader - Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register."]
6pub type L1_ICACHE0_TAG_OBJECT_R = crate::BitReader;
7#[doc = "Field `L1_ICACHE0_TAG_OBJECT` writer - Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register."]
8pub type L1_ICACHE0_TAG_OBJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `L1_ICACHE1_TAG_OBJECT` reader - Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register."]
10pub type L1_ICACHE1_TAG_OBJECT_R = crate::BitReader;
11#[doc = "Field `L1_ICACHE1_TAG_OBJECT` writer - Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register."]
12pub type L1_ICACHE1_TAG_OBJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `L1_ICACHE2_TAG_OBJECT` reader - Reserved"]
14pub type L1_ICACHE2_TAG_OBJECT_R = crate::BitReader;
15#[doc = "Field `L1_ICACHE3_TAG_OBJECT` reader - Reserved"]
16pub type L1_ICACHE3_TAG_OBJECT_R = crate::BitReader;
17#[doc = "Field `L1_DCACHE_TAG_OBJECT` reader - Set this bit to set L1-DCache tag memory as object. This bit should be onehot with the others fields inside this register."]
18pub type L1_DCACHE_TAG_OBJECT_R = crate::BitReader;
19#[doc = "Field `L1_DCACHE_TAG_OBJECT` writer - Set this bit to set L1-DCache tag memory as object. This bit should be onehot with the others fields inside this register."]
20pub type L1_DCACHE_TAG_OBJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `L1_ICACHE0_MEM_OBJECT` reader - Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register."]
22pub type L1_ICACHE0_MEM_OBJECT_R = crate::BitReader;
23#[doc = "Field `L1_ICACHE0_MEM_OBJECT` writer - Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register."]
24pub type L1_ICACHE0_MEM_OBJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `L1_ICACHE1_MEM_OBJECT` reader - Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register."]
26pub type L1_ICACHE1_MEM_OBJECT_R = crate::BitReader;
27#[doc = "Field `L1_ICACHE1_MEM_OBJECT` writer - Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register."]
28pub type L1_ICACHE1_MEM_OBJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `L1_ICACHE2_MEM_OBJECT` reader - Reserved"]
30pub type L1_ICACHE2_MEM_OBJECT_R = crate::BitReader;
31#[doc = "Field `L1_ICACHE3_MEM_OBJECT` reader - Reserved"]
32pub type L1_ICACHE3_MEM_OBJECT_R = crate::BitReader;
33#[doc = "Field `L1_DCACHE_MEM_OBJECT` reader - Set this bit to set L1-DCache data memory as object. This bit should be onehot with the others fields inside this register."]
34pub type L1_DCACHE_MEM_OBJECT_R = crate::BitReader;
35#[doc = "Field `L1_DCACHE_MEM_OBJECT` writer - Set this bit to set L1-DCache data memory as object. This bit should be onehot with the others fields inside this register."]
36pub type L1_DCACHE_MEM_OBJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38 #[doc = "Bit 0 - Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register."]
39 #[inline(always)]
40 pub fn l1_icache0_tag_object(&self) -> L1_ICACHE0_TAG_OBJECT_R {
41 L1_ICACHE0_TAG_OBJECT_R::new((self.bits & 1) != 0)
42 }
43 #[doc = "Bit 1 - Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register."]
44 #[inline(always)]
45 pub fn l1_icache1_tag_object(&self) -> L1_ICACHE1_TAG_OBJECT_R {
46 L1_ICACHE1_TAG_OBJECT_R::new(((self.bits >> 1) & 1) != 0)
47 }
48 #[doc = "Bit 2 - Reserved"]
49 #[inline(always)]
50 pub fn l1_icache2_tag_object(&self) -> L1_ICACHE2_TAG_OBJECT_R {
51 L1_ICACHE2_TAG_OBJECT_R::new(((self.bits >> 2) & 1) != 0)
52 }
53 #[doc = "Bit 3 - Reserved"]
54 #[inline(always)]
55 pub fn l1_icache3_tag_object(&self) -> L1_ICACHE3_TAG_OBJECT_R {
56 L1_ICACHE3_TAG_OBJECT_R::new(((self.bits >> 3) & 1) != 0)
57 }
58 #[doc = "Bit 4 - Set this bit to set L1-DCache tag memory as object. This bit should be onehot with the others fields inside this register."]
59 #[inline(always)]
60 pub fn l1_dcache_tag_object(&self) -> L1_DCACHE_TAG_OBJECT_R {
61 L1_DCACHE_TAG_OBJECT_R::new(((self.bits >> 4) & 1) != 0)
62 }
63 #[doc = "Bit 6 - Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register."]
64 #[inline(always)]
65 pub fn l1_icache0_mem_object(&self) -> L1_ICACHE0_MEM_OBJECT_R {
66 L1_ICACHE0_MEM_OBJECT_R::new(((self.bits >> 6) & 1) != 0)
67 }
68 #[doc = "Bit 7 - Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register."]
69 #[inline(always)]
70 pub fn l1_icache1_mem_object(&self) -> L1_ICACHE1_MEM_OBJECT_R {
71 L1_ICACHE1_MEM_OBJECT_R::new(((self.bits >> 7) & 1) != 0)
72 }
73 #[doc = "Bit 8 - Reserved"]
74 #[inline(always)]
75 pub fn l1_icache2_mem_object(&self) -> L1_ICACHE2_MEM_OBJECT_R {
76 L1_ICACHE2_MEM_OBJECT_R::new(((self.bits >> 8) & 1) != 0)
77 }
78 #[doc = "Bit 9 - Reserved"]
79 #[inline(always)]
80 pub fn l1_icache3_mem_object(&self) -> L1_ICACHE3_MEM_OBJECT_R {
81 L1_ICACHE3_MEM_OBJECT_R::new(((self.bits >> 9) & 1) != 0)
82 }
83 #[doc = "Bit 10 - Set this bit to set L1-DCache data memory as object. This bit should be onehot with the others fields inside this register."]
84 #[inline(always)]
85 pub fn l1_dcache_mem_object(&self) -> L1_DCACHE_MEM_OBJECT_R {
86 L1_DCACHE_MEM_OBJECT_R::new(((self.bits >> 10) & 1) != 0)
87 }
88}
89#[cfg(feature = "impl-register-debug")]
90impl core::fmt::Debug for R {
91 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
92 f.debug_struct("L1_CACHE_OBJECT_CTRL")
93 .field(
94 "l1_icache0_tag_object",
95 &format_args!("{}", self.l1_icache0_tag_object().bit()),
96 )
97 .field(
98 "l1_icache1_tag_object",
99 &format_args!("{}", self.l1_icache1_tag_object().bit()),
100 )
101 .field(
102 "l1_icache2_tag_object",
103 &format_args!("{}", self.l1_icache2_tag_object().bit()),
104 )
105 .field(
106 "l1_icache3_tag_object",
107 &format_args!("{}", self.l1_icache3_tag_object().bit()),
108 )
109 .field(
110 "l1_dcache_tag_object",
111 &format_args!("{}", self.l1_dcache_tag_object().bit()),
112 )
113 .field(
114 "l1_icache0_mem_object",
115 &format_args!("{}", self.l1_icache0_mem_object().bit()),
116 )
117 .field(
118 "l1_icache1_mem_object",
119 &format_args!("{}", self.l1_icache1_mem_object().bit()),
120 )
121 .field(
122 "l1_icache2_mem_object",
123 &format_args!("{}", self.l1_icache2_mem_object().bit()),
124 )
125 .field(
126 "l1_icache3_mem_object",
127 &format_args!("{}", self.l1_icache3_mem_object().bit()),
128 )
129 .field(
130 "l1_dcache_mem_object",
131 &format_args!("{}", self.l1_dcache_mem_object().bit()),
132 )
133 .finish()
134 }
135}
136#[cfg(feature = "impl-register-debug")]
137impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_OBJECT_CTRL_SPEC> {
138 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
139 core::fmt::Debug::fmt(&self.read(), f)
140 }
141}
142impl W {
143 #[doc = "Bit 0 - Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register."]
144 #[inline(always)]
145 #[must_use]
146 pub fn l1_icache0_tag_object(&mut self) -> L1_ICACHE0_TAG_OBJECT_W<L1_CACHE_OBJECT_CTRL_SPEC> {
147 L1_ICACHE0_TAG_OBJECT_W::new(self, 0)
148 }
149 #[doc = "Bit 1 - Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register."]
150 #[inline(always)]
151 #[must_use]
152 pub fn l1_icache1_tag_object(&mut self) -> L1_ICACHE1_TAG_OBJECT_W<L1_CACHE_OBJECT_CTRL_SPEC> {
153 L1_ICACHE1_TAG_OBJECT_W::new(self, 1)
154 }
155 #[doc = "Bit 4 - Set this bit to set L1-DCache tag memory as object. This bit should be onehot with the others fields inside this register."]
156 #[inline(always)]
157 #[must_use]
158 pub fn l1_dcache_tag_object(&mut self) -> L1_DCACHE_TAG_OBJECT_W<L1_CACHE_OBJECT_CTRL_SPEC> {
159 L1_DCACHE_TAG_OBJECT_W::new(self, 4)
160 }
161 #[doc = "Bit 6 - Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register."]
162 #[inline(always)]
163 #[must_use]
164 pub fn l1_icache0_mem_object(&mut self) -> L1_ICACHE0_MEM_OBJECT_W<L1_CACHE_OBJECT_CTRL_SPEC> {
165 L1_ICACHE0_MEM_OBJECT_W::new(self, 6)
166 }
167 #[doc = "Bit 7 - Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register."]
168 #[inline(always)]
169 #[must_use]
170 pub fn l1_icache1_mem_object(&mut self) -> L1_ICACHE1_MEM_OBJECT_W<L1_CACHE_OBJECT_CTRL_SPEC> {
171 L1_ICACHE1_MEM_OBJECT_W::new(self, 7)
172 }
173 #[doc = "Bit 10 - Set this bit to set L1-DCache data memory as object. This bit should be onehot with the others fields inside this register."]
174 #[inline(always)]
175 #[must_use]
176 pub fn l1_dcache_mem_object(&mut self) -> L1_DCACHE_MEM_OBJECT_W<L1_CACHE_OBJECT_CTRL_SPEC> {
177 L1_DCACHE_MEM_OBJECT_W::new(self, 10)
178 }
179}
180#[doc = "Cache Tag and Data memory Object control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_object_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_object_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
181pub struct L1_CACHE_OBJECT_CTRL_SPEC;
182impl crate::RegisterSpec for L1_CACHE_OBJECT_CTRL_SPEC {
183 type Ux = u32;
184}
185#[doc = "`read()` method returns [`l1_cache_object_ctrl::R`](R) reader structure"]
186impl crate::Readable for L1_CACHE_OBJECT_CTRL_SPEC {}
187#[doc = "`write(|w| ..)` method takes [`l1_cache_object_ctrl::W`](W) writer structure"]
188impl crate::Writable for L1_CACHE_OBJECT_CTRL_SPEC {
189 type Safety = crate::Unsafe;
190 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
191 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
192}
193#[doc = "`reset()` method sets L1_CACHE_OBJECT_CTRL to value 0"]
194impl crate::Resettable for L1_CACHE_OBJECT_CTRL_SPEC {
195 const RESET_VALUE: u32 = 0;
196}