esp32p4/cache/
l1_cache_atomic_conf.rs

1#[doc = "Register `L1_CACHE_ATOMIC_CONF` reader"]
2pub type R = crate::R<L1_CACHE_ATOMIC_CONF_SPEC>;
3#[doc = "Register `L1_CACHE_ATOMIC_CONF` writer"]
4pub type W = crate::W<L1_CACHE_ATOMIC_CONF_SPEC>;
5#[doc = "Field `L1_DCACHE_ATOMIC_EN` reader - The bit is used to enable atomic feature on L1-DCache when multiple cores access L1-DCache. 1: disable, 1: enable."]
6pub type L1_DCACHE_ATOMIC_EN_R = crate::BitReader;
7#[doc = "Field `L1_DCACHE_ATOMIC_EN` writer - The bit is used to enable atomic feature on L1-DCache when multiple cores access L1-DCache. 1: disable, 1: enable."]
8pub type L1_DCACHE_ATOMIC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9impl R {
10    #[doc = "Bit 0 - The bit is used to enable atomic feature on L1-DCache when multiple cores access L1-DCache. 1: disable, 1: enable."]
11    #[inline(always)]
12    pub fn l1_dcache_atomic_en(&self) -> L1_DCACHE_ATOMIC_EN_R {
13        L1_DCACHE_ATOMIC_EN_R::new((self.bits & 1) != 0)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("L1_CACHE_ATOMIC_CONF")
20            .field(
21                "l1_dcache_atomic_en",
22                &format_args!("{}", self.l1_dcache_atomic_en().bit()),
23            )
24            .finish()
25    }
26}
27#[cfg(feature = "impl-register-debug")]
28impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ATOMIC_CONF_SPEC> {
29    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
30        core::fmt::Debug::fmt(&self.read(), f)
31    }
32}
33impl W {
34    #[doc = "Bit 0 - The bit is used to enable atomic feature on L1-DCache when multiple cores access L1-DCache. 1: disable, 1: enable."]
35    #[inline(always)]
36    #[must_use]
37    pub fn l1_dcache_atomic_en(&mut self) -> L1_DCACHE_ATOMIC_EN_W<L1_CACHE_ATOMIC_CONF_SPEC> {
38        L1_DCACHE_ATOMIC_EN_W::new(self, 0)
39    }
40}
41#[doc = "L1 Cache atomic feature configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_atomic_conf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_atomic_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
42pub struct L1_CACHE_ATOMIC_CONF_SPEC;
43impl crate::RegisterSpec for L1_CACHE_ATOMIC_CONF_SPEC {
44    type Ux = u32;
45}
46#[doc = "`read()` method returns [`l1_cache_atomic_conf::R`](R) reader structure"]
47impl crate::Readable for L1_CACHE_ATOMIC_CONF_SPEC {}
48#[doc = "`write(|w| ..)` method takes [`l1_cache_atomic_conf::W`](W) writer structure"]
49impl crate::Writable for L1_CACHE_ATOMIC_CONF_SPEC {
50    type Safety = crate::Unsafe;
51    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
52    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
53}
54#[doc = "`reset()` method sets L1_CACHE_ATOMIC_CONF to value 0x01"]
55impl crate::Resettable for L1_CACHE_ATOMIC_CONF_SPEC {
56    const RESET_VALUE: u32 = 0x01;
57}
esp32p4/cache/l1_cache_atomic_conf.rs

esp32p4/cache/
l1_cache_atomic_conf.rs
