esp32p4/axi_dma/
in_mem_conf.rs1#[doc = "Register `IN_MEM_CONF` reader"]
2pub type R = crate::R<IN_MEM_CONF_SPEC>;
3#[doc = "Register `IN_MEM_CONF` writer"]
4pub type W = crate::W<IN_MEM_CONF_SPEC>;
5#[doc = "Field `IN_MEM_CLK_FORCE_EN` reader - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA."]
6pub type IN_MEM_CLK_FORCE_EN_R = crate::BitReader;
7#[doc = "Field `IN_MEM_CLK_FORCE_EN` writer - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA."]
8pub type IN_MEM_CLK_FORCE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `IN_MEM_FORCE_PU` reader - Force power up ram"]
10pub type IN_MEM_FORCE_PU_R = crate::BitReader;
11#[doc = "Field `IN_MEM_FORCE_PU` writer - Force power up ram"]
12pub type IN_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `IN_MEM_FORCE_PD` reader - Force power down ram"]
14pub type IN_MEM_FORCE_PD_R = crate::BitReader;
15#[doc = "Field `IN_MEM_FORCE_PD` writer - Force power down ram"]
16pub type IN_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `OUT_MEM_CLK_FORCE_EN` reader - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA."]
18pub type OUT_MEM_CLK_FORCE_EN_R = crate::BitReader;
19#[doc = "Field `OUT_MEM_CLK_FORCE_EN` writer - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA."]
20pub type OUT_MEM_CLK_FORCE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `OUT_MEM_FORCE_PU` reader - Force power up ram"]
22pub type OUT_MEM_FORCE_PU_R = crate::BitReader;
23#[doc = "Field `OUT_MEM_FORCE_PU` writer - Force power up ram"]
24pub type OUT_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `OUT_MEM_FORCE_PD` reader - Force power down ram"]
26pub type OUT_MEM_FORCE_PD_R = crate::BitReader;
27#[doc = "Field `OUT_MEM_FORCE_PD` writer - Force power down ram"]
28pub type OUT_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30 #[doc = "Bit 0 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA."]
31 #[inline(always)]
32 pub fn in_mem_clk_force_en(&self) -> IN_MEM_CLK_FORCE_EN_R {
33 IN_MEM_CLK_FORCE_EN_R::new((self.bits & 1) != 0)
34 }
35 #[doc = "Bit 1 - Force power up ram"]
36 #[inline(always)]
37 pub fn in_mem_force_pu(&self) -> IN_MEM_FORCE_PU_R {
38 IN_MEM_FORCE_PU_R::new(((self.bits >> 1) & 1) != 0)
39 }
40 #[doc = "Bit 2 - Force power down ram"]
41 #[inline(always)]
42 pub fn in_mem_force_pd(&self) -> IN_MEM_FORCE_PD_R {
43 IN_MEM_FORCE_PD_R::new(((self.bits >> 2) & 1) != 0)
44 }
45 #[doc = "Bit 3 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA."]
46 #[inline(always)]
47 pub fn out_mem_clk_force_en(&self) -> OUT_MEM_CLK_FORCE_EN_R {
48 OUT_MEM_CLK_FORCE_EN_R::new(((self.bits >> 3) & 1) != 0)
49 }
50 #[doc = "Bit 4 - Force power up ram"]
51 #[inline(always)]
52 pub fn out_mem_force_pu(&self) -> OUT_MEM_FORCE_PU_R {
53 OUT_MEM_FORCE_PU_R::new(((self.bits >> 4) & 1) != 0)
54 }
55 #[doc = "Bit 5 - Force power down ram"]
56 #[inline(always)]
57 pub fn out_mem_force_pd(&self) -> OUT_MEM_FORCE_PD_R {
58 OUT_MEM_FORCE_PD_R::new(((self.bits >> 5) & 1) != 0)
59 }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64 f.debug_struct("IN_MEM_CONF")
65 .field(
66 "in_mem_clk_force_en",
67 &format_args!("{}", self.in_mem_clk_force_en().bit()),
68 )
69 .field(
70 "in_mem_force_pu",
71 &format_args!("{}", self.in_mem_force_pu().bit()),
72 )
73 .field(
74 "in_mem_force_pd",
75 &format_args!("{}", self.in_mem_force_pd().bit()),
76 )
77 .field(
78 "out_mem_clk_force_en",
79 &format_args!("{}", self.out_mem_clk_force_en().bit()),
80 )
81 .field(
82 "out_mem_force_pu",
83 &format_args!("{}", self.out_mem_force_pu().bit()),
84 )
85 .field(
86 "out_mem_force_pd",
87 &format_args!("{}", self.out_mem_force_pd().bit()),
88 )
89 .finish()
90 }
91}
92#[cfg(feature = "impl-register-debug")]
93impl core::fmt::Debug for crate::generic::Reg<IN_MEM_CONF_SPEC> {
94 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
95 core::fmt::Debug::fmt(&self.read(), f)
96 }
97}
98impl W {
99 #[doc = "Bit 0 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA."]
100 #[inline(always)]
101 #[must_use]
102 pub fn in_mem_clk_force_en(&mut self) -> IN_MEM_CLK_FORCE_EN_W<IN_MEM_CONF_SPEC> {
103 IN_MEM_CLK_FORCE_EN_W::new(self, 0)
104 }
105 #[doc = "Bit 1 - Force power up ram"]
106 #[inline(always)]
107 #[must_use]
108 pub fn in_mem_force_pu(&mut self) -> IN_MEM_FORCE_PU_W<IN_MEM_CONF_SPEC> {
109 IN_MEM_FORCE_PU_W::new(self, 1)
110 }
111 #[doc = "Bit 2 - Force power down ram"]
112 #[inline(always)]
113 #[must_use]
114 pub fn in_mem_force_pd(&mut self) -> IN_MEM_FORCE_PD_W<IN_MEM_CONF_SPEC> {
115 IN_MEM_FORCE_PD_W::new(self, 2)
116 }
117 #[doc = "Bit 3 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA."]
118 #[inline(always)]
119 #[must_use]
120 pub fn out_mem_clk_force_en(&mut self) -> OUT_MEM_CLK_FORCE_EN_W<IN_MEM_CONF_SPEC> {
121 OUT_MEM_CLK_FORCE_EN_W::new(self, 3)
122 }
123 #[doc = "Bit 4 - Force power up ram"]
124 #[inline(always)]
125 #[must_use]
126 pub fn out_mem_force_pu(&mut self) -> OUT_MEM_FORCE_PU_W<IN_MEM_CONF_SPEC> {
127 OUT_MEM_FORCE_PU_W::new(self, 4)
128 }
129 #[doc = "Bit 5 - Force power down ram"]
130 #[inline(always)]
131 #[must_use]
132 pub fn out_mem_force_pd(&mut self) -> OUT_MEM_FORCE_PD_W<IN_MEM_CONF_SPEC> {
133 OUT_MEM_FORCE_PD_W::new(self, 5)
134 }
135}
136#[doc = "Mem power configure register of Rx channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_mem_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_mem_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
137pub struct IN_MEM_CONF_SPEC;
138impl crate::RegisterSpec for IN_MEM_CONF_SPEC {
139 type Ux = u32;
140}
141#[doc = "`read()` method returns [`in_mem_conf::R`](R) reader structure"]
142impl crate::Readable for IN_MEM_CONF_SPEC {}
143#[doc = "`write(|w| ..)` method takes [`in_mem_conf::W`](W) writer structure"]
144impl crate::Writable for IN_MEM_CONF_SPEC {
145 type Safety = crate::Unsafe;
146 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
147 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
148}
149#[doc = "`reset()` method sets IN_MEM_CONF to value 0"]
150impl crate::Resettable for IN_MEM_CONF_SPEC {
151 const RESET_VALUE: u32 = 0;
152}