esp32p4/ahb_dma/in_int_ch/
ena.rs

1#[doc = "Register `ENA` reader"]
2pub type R = crate::R<ENA_SPEC>;
3#[doc = "Register `ENA` writer"]
4pub type W = crate::W<ENA_SPEC>;
5#[doc = "Field `IN_DONE` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
6pub type IN_DONE_R = crate::BitReader;
7#[doc = "Field `IN_DONE` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
8pub type IN_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `IN_SUC_EOF` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."]
10pub type IN_SUC_EOF_R = crate::BitReader;
11#[doc = "Field `IN_SUC_EOF` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."]
12pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `IN_ERR_EOF` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."]
14pub type IN_ERR_EOF_R = crate::BitReader;
15#[doc = "Field `IN_ERR_EOF` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."]
16pub type IN_ERR_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `IN_DSCR_ERR` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."]
18pub type IN_DSCR_ERR_R = crate::BitReader;
19#[doc = "Field `IN_DSCR_ERR` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."]
20pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `IN_DSCR_EMPTY` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."]
22pub type IN_DSCR_EMPTY_R = crate::BitReader;
23#[doc = "Field `IN_DSCR_EMPTY` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."]
24pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `INFIFO_OVF` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."]
26pub type INFIFO_OVF_R = crate::BitReader;
27#[doc = "Field `INFIFO_OVF` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."]
28pub type INFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `INFIFO_UDF` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."]
30pub type INFIFO_UDF_R = crate::BitReader;
31#[doc = "Field `INFIFO_UDF` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."]
32pub type INFIFO_UDF_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34    #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
35    #[inline(always)]
36    pub fn in_done(&self) -> IN_DONE_R {
37        IN_DONE_R::new((self.bits & 1) != 0)
38    }
39    #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."]
40    #[inline(always)]
41    pub fn in_suc_eof(&self) -> IN_SUC_EOF_R {
42        IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0)
43    }
44    #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."]
45    #[inline(always)]
46    pub fn in_err_eof(&self) -> IN_ERR_EOF_R {
47        IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0)
48    }
49    #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."]
50    #[inline(always)]
51    pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R {
52        IN_DSCR_ERR_R::new(((self.bits >> 3) & 1) != 0)
53    }
54    #[doc = "Bit 4 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."]
55    #[inline(always)]
56    pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R {
57        IN_DSCR_EMPTY_R::new(((self.bits >> 4) & 1) != 0)
58    }
59    #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."]
60    #[inline(always)]
61    pub fn infifo_ovf(&self) -> INFIFO_OVF_R {
62        INFIFO_OVF_R::new(((self.bits >> 5) & 1) != 0)
63    }
64    #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."]
65    #[inline(always)]
66    pub fn infifo_udf(&self) -> INFIFO_UDF_R {
67        INFIFO_UDF_R::new(((self.bits >> 6) & 1) != 0)
68    }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73        f.debug_struct("ENA")
74            .field("in_done", &format_args!("{}", self.in_done().bit()))
75            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
76            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
77            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
78            .field(
79                "in_dscr_empty",
80                &format_args!("{}", self.in_dscr_empty().bit()),
81            )
82            .field("infifo_ovf", &format_args!("{}", self.infifo_ovf().bit()))
83            .field("infifo_udf", &format_args!("{}", self.infifo_udf().bit()))
84            .finish()
85    }
86}
87#[cfg(feature = "impl-register-debug")]
88impl core::fmt::Debug for crate::generic::Reg<ENA_SPEC> {
89    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
90        core::fmt::Debug::fmt(&self.read(), f)
91    }
92}
93impl W {
94    #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
95    #[inline(always)]
96    #[must_use]
97    pub fn in_done(&mut self) -> IN_DONE_W<ENA_SPEC> {
98        IN_DONE_W::new(self, 0)
99    }
100    #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."]
101    #[inline(always)]
102    #[must_use]
103    pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<ENA_SPEC> {
104        IN_SUC_EOF_W::new(self, 1)
105    }
106    #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."]
107    #[inline(always)]
108    #[must_use]
109    pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<ENA_SPEC> {
110        IN_ERR_EOF_W::new(self, 2)
111    }
112    #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."]
113    #[inline(always)]
114    #[must_use]
115    pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<ENA_SPEC> {
116        IN_DSCR_ERR_W::new(self, 3)
117    }
118    #[doc = "Bit 4 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."]
119    #[inline(always)]
120    #[must_use]
121    pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<ENA_SPEC> {
122        IN_DSCR_EMPTY_W::new(self, 4)
123    }
124    #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."]
125    #[inline(always)]
126    #[must_use]
127    pub fn infifo_ovf(&mut self) -> INFIFO_OVF_W<ENA_SPEC> {
128        INFIFO_OVF_W::new(self, 5)
129    }
130    #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."]
131    #[inline(always)]
132    #[must_use]
133    pub fn infifo_udf(&mut self) -> INFIFO_UDF_W<ENA_SPEC> {
134        INFIFO_UDF_W::new(self, 6)
135    }
136}
137#[doc = "Interrupt enable bits of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ena::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
138pub struct ENA_SPEC;
139impl crate::RegisterSpec for ENA_SPEC {
140    type Ux = u32;
141}
142#[doc = "`read()` method returns [`ena::R`](R) reader structure"]
143impl crate::Readable for ENA_SPEC {}
144#[doc = "`write(|w| ..)` method takes [`ena::W`](W) writer structure"]
145impl crate::Writable for ENA_SPEC {
146    type Safety = crate::Unsafe;
147    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
148    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
149}
150#[doc = "`reset()` method sets ENA to value 0"]
151impl crate::Resettable for ENA_SPEC {
152    const RESET_VALUE: u32 = 0;
153}
esp32p4/ahb_dma/in_int_ch/ena.rs

esp32p4/ahb_dma/in_int_ch/
ena.rs
