1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `RX_START` reader - Set this bit to enable the interrupt of UHCI_RX_START_INT."]
6pub type RX_START_R = crate::BitReader;
7#[doc = "Field `RX_START` writer - Set this bit to enable the interrupt of UHCI_RX_START_INT."]
8pub type RX_START_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TX_START` reader - Set this bit to enable the interrupt of UHCI_TX_START_INT."]
10pub type TX_START_R = crate::BitReader;
11#[doc = "Field `TX_START` writer - Set this bit to enable the interrupt of UHCI_TX_START_INT."]
12pub type TX_START_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RX_HUNG` reader - Set this bit to enable the interrupt of UHCI_RX_HUNG_INT."]
14pub type RX_HUNG_R = crate::BitReader;
15#[doc = "Field `RX_HUNG` writer - Set this bit to enable the interrupt of UHCI_RX_HUNG_INT."]
16pub type RX_HUNG_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TX_HUNG` reader - Set this bit to enable the interrupt of UHCI_TX_HUNG_INT."]
18pub type TX_HUNG_R = crate::BitReader;
19#[doc = "Field `TX_HUNG` writer - Set this bit to enable the interrupt of UHCI_TX_HUNG_INT."]
20pub type TX_HUNG_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SEND_S_REG_Q` reader - Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT."]
22pub type SEND_S_REG_Q_R = crate::BitReader;
23#[doc = "Field `SEND_S_REG_Q` writer - Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT."]
24pub type SEND_S_REG_Q_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SEND_A_REG_Q` reader - Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT."]
26pub type SEND_A_REG_Q_R = crate::BitReader;
27#[doc = "Field `SEND_A_REG_Q` writer - Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT."]
28pub type SEND_A_REG_Q_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `OUTLINK_EOF_ERR` reader - Set this bit to enable the interrupt of UHCI_OUT_EOF_INT."]
30pub type OUTLINK_EOF_ERR_R = crate::BitReader;
31#[doc = "Field `OUTLINK_EOF_ERR` writer - Set this bit to enable the interrupt of UHCI_OUT_EOF_INT."]
32pub type OUTLINK_EOF_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `APP_CTRL0` reader - Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT."]
34pub type APP_CTRL0_R = crate::BitReader;
35#[doc = "Field `APP_CTRL0` writer - Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT."]
36pub type APP_CTRL0_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `APP_CTRL1` reader - Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT."]
38pub type APP_CTRL1_R = crate::BitReader;
39#[doc = "Field `APP_CTRL1` writer - Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT."]
40pub type APP_CTRL1_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42 #[doc = "Bit 0 - Set this bit to enable the interrupt of UHCI_RX_START_INT."]
43 #[inline(always)]
44 pub fn rx_start(&self) -> RX_START_R {
45 RX_START_R::new((self.bits & 1) != 0)
46 }
47 #[doc = "Bit 1 - Set this bit to enable the interrupt of UHCI_TX_START_INT."]
48 #[inline(always)]
49 pub fn tx_start(&self) -> TX_START_R {
50 TX_START_R::new(((self.bits >> 1) & 1) != 0)
51 }
52 #[doc = "Bit 2 - Set this bit to enable the interrupt of UHCI_RX_HUNG_INT."]
53 #[inline(always)]
54 pub fn rx_hung(&self) -> RX_HUNG_R {
55 RX_HUNG_R::new(((self.bits >> 2) & 1) != 0)
56 }
57 #[doc = "Bit 3 - Set this bit to enable the interrupt of UHCI_TX_HUNG_INT."]
58 #[inline(always)]
59 pub fn tx_hung(&self) -> TX_HUNG_R {
60 TX_HUNG_R::new(((self.bits >> 3) & 1) != 0)
61 }
62 #[doc = "Bit 4 - Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT."]
63 #[inline(always)]
64 pub fn send_s_reg_q(&self) -> SEND_S_REG_Q_R {
65 SEND_S_REG_Q_R::new(((self.bits >> 4) & 1) != 0)
66 }
67 #[doc = "Bit 5 - Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT."]
68 #[inline(always)]
69 pub fn send_a_reg_q(&self) -> SEND_A_REG_Q_R {
70 SEND_A_REG_Q_R::new(((self.bits >> 5) & 1) != 0)
71 }
72 #[doc = "Bit 6 - Set this bit to enable the interrupt of UHCI_OUT_EOF_INT."]
73 #[inline(always)]
74 pub fn outlink_eof_err(&self) -> OUTLINK_EOF_ERR_R {
75 OUTLINK_EOF_ERR_R::new(((self.bits >> 6) & 1) != 0)
76 }
77 #[doc = "Bit 7 - Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT."]
78 #[inline(always)]
79 pub fn app_ctrl0(&self) -> APP_CTRL0_R {
80 APP_CTRL0_R::new(((self.bits >> 7) & 1) != 0)
81 }
82 #[doc = "Bit 8 - Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT."]
83 #[inline(always)]
84 pub fn app_ctrl1(&self) -> APP_CTRL1_R {
85 APP_CTRL1_R::new(((self.bits >> 8) & 1) != 0)
86 }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91 f.debug_struct("INT_ENA")
92 .field("rx_start", &format_args!("{}", self.rx_start().bit()))
93 .field("tx_start", &format_args!("{}", self.tx_start().bit()))
94 .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
95 .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
96 .field(
97 "send_s_reg_q",
98 &format_args!("{}", self.send_s_reg_q().bit()),
99 )
100 .field(
101 "send_a_reg_q",
102 &format_args!("{}", self.send_a_reg_q().bit()),
103 )
104 .field(
105 "outlink_eof_err",
106 &format_args!("{}", self.outlink_eof_err().bit()),
107 )
108 .field("app_ctrl0", &format_args!("{}", self.app_ctrl0().bit()))
109 .field("app_ctrl1", &format_args!("{}", self.app_ctrl1().bit()))
110 .finish()
111 }
112}
113#[cfg(feature = "impl-register-debug")]
114impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
115 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
116 core::fmt::Debug::fmt(&self.read(), f)
117 }
118}
119impl W {
120 #[doc = "Bit 0 - Set this bit to enable the interrupt of UHCI_RX_START_INT."]
121 #[inline(always)]
122 #[must_use]
123 pub fn rx_start(&mut self) -> RX_START_W<INT_ENA_SPEC> {
124 RX_START_W::new(self, 0)
125 }
126 #[doc = "Bit 1 - Set this bit to enable the interrupt of UHCI_TX_START_INT."]
127 #[inline(always)]
128 #[must_use]
129 pub fn tx_start(&mut self) -> TX_START_W<INT_ENA_SPEC> {
130 TX_START_W::new(self, 1)
131 }
132 #[doc = "Bit 2 - Set this bit to enable the interrupt of UHCI_RX_HUNG_INT."]
133 #[inline(always)]
134 #[must_use]
135 pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_ENA_SPEC> {
136 RX_HUNG_W::new(self, 2)
137 }
138 #[doc = "Bit 3 - Set this bit to enable the interrupt of UHCI_TX_HUNG_INT."]
139 #[inline(always)]
140 #[must_use]
141 pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_ENA_SPEC> {
142 TX_HUNG_W::new(self, 3)
143 }
144 #[doc = "Bit 4 - Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT."]
145 #[inline(always)]
146 #[must_use]
147 pub fn send_s_reg_q(&mut self) -> SEND_S_REG_Q_W<INT_ENA_SPEC> {
148 SEND_S_REG_Q_W::new(self, 4)
149 }
150 #[doc = "Bit 5 - Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT."]
151 #[inline(always)]
152 #[must_use]
153 pub fn send_a_reg_q(&mut self) -> SEND_A_REG_Q_W<INT_ENA_SPEC> {
154 SEND_A_REG_Q_W::new(self, 5)
155 }
156 #[doc = "Bit 6 - Set this bit to enable the interrupt of UHCI_OUT_EOF_INT."]
157 #[inline(always)]
158 #[must_use]
159 pub fn outlink_eof_err(&mut self) -> OUTLINK_EOF_ERR_W<INT_ENA_SPEC> {
160 OUTLINK_EOF_ERR_W::new(self, 6)
161 }
162 #[doc = "Bit 7 - Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT."]
163 #[inline(always)]
164 #[must_use]
165 pub fn app_ctrl0(&mut self) -> APP_CTRL0_W<INT_ENA_SPEC> {
166 APP_CTRL0_W::new(self, 7)
167 }
168 #[doc = "Bit 8 - Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT."]
169 #[inline(always)]
170 #[must_use]
171 pub fn app_ctrl1(&mut self) -> APP_CTRL1_W<INT_ENA_SPEC> {
172 APP_CTRL1_W::new(self, 8)
173 }
174}
175#[doc = "UHCI Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
176pub struct INT_ENA_SPEC;
177impl crate::RegisterSpec for INT_ENA_SPEC {
178 type Ux = u32;
179}
180#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
181impl crate::Readable for INT_ENA_SPEC {}
182#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
183impl crate::Writable for INT_ENA_SPEC {
184 type Safety = crate::Unsafe;
185 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
186 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
187}
188#[doc = "`reset()` method sets INT_ENA to value 0"]
189impl crate::Resettable for INT_ENA_SPEC {
190 const RESET_VALUE: u32 = 0;
191}