esp32p4/uart0/
clk_conf.rs

1#[doc = "Register `CLK_CONF` reader"]
2pub type R = crate::R<CLK_CONF_SPEC>;
3#[doc = "Register `CLK_CONF` writer"]
4pub type W = crate::W<CLK_CONF_SPEC>;
5#[doc = "Field `TX_SCLK_EN` reader - Set this bit to enable UART Tx clock."]
6pub type TX_SCLK_EN_R = crate::BitReader;
7#[doc = "Field `TX_SCLK_EN` writer - Set this bit to enable UART Tx clock."]
8pub type TX_SCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `RX_SCLK_EN` reader - Set this bit to enable UART Rx clock."]
10pub type RX_SCLK_EN_R = crate::BitReader;
11#[doc = "Field `RX_SCLK_EN` writer - Set this bit to enable UART Rx clock."]
12pub type RX_SCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TX_RST_CORE` reader - Write 1 then write 0 to this bit to reset UART Tx."]
14pub type TX_RST_CORE_R = crate::BitReader;
15#[doc = "Field `TX_RST_CORE` writer - Write 1 then write 0 to this bit to reset UART Tx."]
16pub type TX_RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RX_RST_CORE` reader - Write 1 then write 0 to this bit to reset UART Rx."]
18pub type RX_RST_CORE_R = crate::BitReader;
19#[doc = "Field `RX_RST_CORE` writer - Write 1 then write 0 to this bit to reset UART Rx."]
20pub type RX_RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 24 - Set this bit to enable UART Tx clock."]
23    #[inline(always)]
24    pub fn tx_sclk_en(&self) -> TX_SCLK_EN_R {
25        TX_SCLK_EN_R::new(((self.bits >> 24) & 1) != 0)
26    }
27    #[doc = "Bit 25 - Set this bit to enable UART Rx clock."]
28    #[inline(always)]
29    pub fn rx_sclk_en(&self) -> RX_SCLK_EN_R {
30        RX_SCLK_EN_R::new(((self.bits >> 25) & 1) != 0)
31    }
32    #[doc = "Bit 26 - Write 1 then write 0 to this bit to reset UART Tx."]
33    #[inline(always)]
34    pub fn tx_rst_core(&self) -> TX_RST_CORE_R {
35        TX_RST_CORE_R::new(((self.bits >> 26) & 1) != 0)
36    }
37    #[doc = "Bit 27 - Write 1 then write 0 to this bit to reset UART Rx."]
38    #[inline(always)]
39    pub fn rx_rst_core(&self) -> RX_RST_CORE_R {
40        RX_RST_CORE_R::new(((self.bits >> 27) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("CLK_CONF")
47            .field("tx_sclk_en", &format_args!("{}", self.tx_sclk_en().bit()))
48            .field("rx_sclk_en", &format_args!("{}", self.rx_sclk_en().bit()))
49            .field("tx_rst_core", &format_args!("{}", self.tx_rst_core().bit()))
50            .field("rx_rst_core", &format_args!("{}", self.rx_rst_core().bit()))
51            .finish()
52    }
53}
54#[cfg(feature = "impl-register-debug")]
55impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
56    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
57        core::fmt::Debug::fmt(&self.read(), f)
58    }
59}
60impl W {
61    #[doc = "Bit 24 - Set this bit to enable UART Tx clock."]
62    #[inline(always)]
63    #[must_use]
64    pub fn tx_sclk_en(&mut self) -> TX_SCLK_EN_W<CLK_CONF_SPEC> {
65        TX_SCLK_EN_W::new(self, 24)
66    }
67    #[doc = "Bit 25 - Set this bit to enable UART Rx clock."]
68    #[inline(always)]
69    #[must_use]
70    pub fn rx_sclk_en(&mut self) -> RX_SCLK_EN_W<CLK_CONF_SPEC> {
71        RX_SCLK_EN_W::new(self, 25)
72    }
73    #[doc = "Bit 26 - Write 1 then write 0 to this bit to reset UART Tx."]
74    #[inline(always)]
75    #[must_use]
76    pub fn tx_rst_core(&mut self) -> TX_RST_CORE_W<CLK_CONF_SPEC> {
77        TX_RST_CORE_W::new(self, 26)
78    }
79    #[doc = "Bit 27 - Write 1 then write 0 to this bit to reset UART Rx."]
80    #[inline(always)]
81    #[must_use]
82    pub fn rx_rst_core(&mut self) -> RX_RST_CORE_W<CLK_CONF_SPEC> {
83        RX_RST_CORE_W::new(self, 27)
84    }
85}
86#[doc = "UART core clock configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_conf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
87pub struct CLK_CONF_SPEC;
88impl crate::RegisterSpec for CLK_CONF_SPEC {
89    type Ux = u32;
90}
91#[doc = "`read()` method returns [`clk_conf::R`](R) reader structure"]
92impl crate::Readable for CLK_CONF_SPEC {}
93#[doc = "`write(|w| ..)` method takes [`clk_conf::W`](W) writer structure"]
94impl crate::Writable for CLK_CONF_SPEC {
95    type Safety = crate::Unsafe;
96    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
97    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
98}
99#[doc = "`reset()` method sets CLK_CONF to value 0x0300_0000"]
100impl crate::Resettable for CLK_CONF_SPEC {
101    const RESET_VALUE: u32 = 0x0300_0000;
102}
esp32p4/uart0/clk_conf.rs

esp32p4/uart0/
clk_conf.rs
