esp32p4/trace0/
intr_raw.rs1#[doc = "Register `INTR_RAW` reader"]
2pub type R = crate::R<INTR_RAW_SPEC>;
3#[doc = "Field `FIFO_OVERFLOW_INTR_RAW` reader - fifo_overflow interrupt status"]
4pub type FIFO_OVERFLOW_INTR_RAW_R = crate::BitReader;
5#[doc = "Field `MEM_FULL_INTR_RAW` reader - mem_full interrupt status"]
6pub type MEM_FULL_INTR_RAW_R = crate::BitReader;
7impl R {
8 #[doc = "Bit 0 - fifo_overflow interrupt status"]
9 #[inline(always)]
10 pub fn fifo_overflow_intr_raw(&self) -> FIFO_OVERFLOW_INTR_RAW_R {
11 FIFO_OVERFLOW_INTR_RAW_R::new((self.bits & 1) != 0)
12 }
13 #[doc = "Bit 1 - mem_full interrupt status"]
14 #[inline(always)]
15 pub fn mem_full_intr_raw(&self) -> MEM_FULL_INTR_RAW_R {
16 MEM_FULL_INTR_RAW_R::new(((self.bits >> 1) & 1) != 0)
17 }
18}
19#[cfg(feature = "impl-register-debug")]
20impl core::fmt::Debug for R {
21 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22 f.debug_struct("INTR_RAW")
23 .field(
24 "fifo_overflow_intr_raw",
25 &format_args!("{}", self.fifo_overflow_intr_raw().bit()),
26 )
27 .field(
28 "mem_full_intr_raw",
29 &format_args!("{}", self.mem_full_intr_raw().bit()),
30 )
31 .finish()
32 }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for crate::generic::Reg<INTR_RAW_SPEC> {
36 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
37 core::fmt::Debug::fmt(&self.read(), f)
38 }
39}
40#[doc = "interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
41pub struct INTR_RAW_SPEC;
42impl crate::RegisterSpec for INTR_RAW_SPEC {
43 type Ux = u32;
44}
45#[doc = "`read()` method returns [`intr_raw::R`](R) reader structure"]
46impl crate::Readable for INTR_RAW_SPEC {}
47#[doc = "`reset()` method sets INTR_RAW to value 0"]
48impl crate::Resettable for INTR_RAW_SPEC {
49 const RESET_VALUE: u32 = 0;
50}