1#[doc = "Register `MISC` reader"]
2pub type R = crate::R<MISC_SPEC>;
3#[doc = "Register `MISC` writer"]
4pub type W = crate::W<MISC_SPEC>;
5#[doc = "Field `CS0_DIS` reader - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
6pub type CS0_DIS_R = crate::BitReader;
7#[doc = "Field `CS0_DIS` writer - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
8pub type CS0_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CS1_DIS` reader - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."]
10pub type CS1_DIS_R = crate::BitReader;
11#[doc = "Field `CS1_DIS` writer - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."]
12pub type CS1_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CS2_DIS` reader - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."]
14pub type CS2_DIS_R = crate::BitReader;
15#[doc = "Field `CS2_DIS` writer - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."]
16pub type CS2_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CK_DIS` reader - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
18pub type CK_DIS_R = crate::BitReader;
19#[doc = "Field `CK_DIS` writer - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
20pub type CK_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `MASTER_CS_POL` reader - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."]
22pub type MASTER_CS_POL_R = crate::FieldReader;
23#[doc = "Field `MASTER_CS_POL` writer - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."]
24pub type MASTER_CS_POL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
25#[doc = "Field `SLAVE_CS_POL` reader - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
26pub type SLAVE_CS_POL_R = crate::BitReader;
27#[doc = "Field `SLAVE_CS_POL` writer - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
28pub type SLAVE_CS_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CK_IDLE_EDGE` reader - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
30pub type CK_IDLE_EDGE_R = crate::BitReader;
31#[doc = "Field `CK_IDLE_EDGE` writer - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
32pub type CK_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CS_KEEP_ACTIVE` reader - spi cs line keep low when the bit is set. Can be configured in CONF state."]
34pub type CS_KEEP_ACTIVE_R = crate::BitReader;
35#[doc = "Field `CS_KEEP_ACTIVE` writer - spi cs line keep low when the bit is set. Can be configured in CONF state."]
36pub type CS_KEEP_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `QUAD_DIN_PIN_SWAP` reader - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state."]
38pub type QUAD_DIN_PIN_SWAP_R = crate::BitReader;
39#[doc = "Field `QUAD_DIN_PIN_SWAP` writer - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state."]
40pub type QUAD_DIN_PIN_SWAP_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42 #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
43 #[inline(always)]
44 pub fn cs0_dis(&self) -> CS0_DIS_R {
45 CS0_DIS_R::new((self.bits & 1) != 0)
46 }
47 #[doc = "Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."]
48 #[inline(always)]
49 pub fn cs1_dis(&self) -> CS1_DIS_R {
50 CS1_DIS_R::new(((self.bits >> 1) & 1) != 0)
51 }
52 #[doc = "Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."]
53 #[inline(always)]
54 pub fn cs2_dis(&self) -> CS2_DIS_R {
55 CS2_DIS_R::new(((self.bits >> 2) & 1) != 0)
56 }
57 #[doc = "Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
58 #[inline(always)]
59 pub fn ck_dis(&self) -> CK_DIS_R {
60 CK_DIS_R::new(((self.bits >> 6) & 1) != 0)
61 }
62 #[doc = "Bits 7:9 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."]
63 #[inline(always)]
64 pub fn master_cs_pol(&self) -> MASTER_CS_POL_R {
65 MASTER_CS_POL_R::new(((self.bits >> 7) & 7) as u8)
66 }
67 #[doc = "Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
68 #[inline(always)]
69 pub fn slave_cs_pol(&self) -> SLAVE_CS_POL_R {
70 SLAVE_CS_POL_R::new(((self.bits >> 23) & 1) != 0)
71 }
72 #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
73 #[inline(always)]
74 pub fn ck_idle_edge(&self) -> CK_IDLE_EDGE_R {
75 CK_IDLE_EDGE_R::new(((self.bits >> 29) & 1) != 0)
76 }
77 #[doc = "Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state."]
78 #[inline(always)]
79 pub fn cs_keep_active(&self) -> CS_KEEP_ACTIVE_R {
80 CS_KEEP_ACTIVE_R::new(((self.bits >> 30) & 1) != 0)
81 }
82 #[doc = "Bit 31 - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state."]
83 #[inline(always)]
84 pub fn quad_din_pin_swap(&self) -> QUAD_DIN_PIN_SWAP_R {
85 QUAD_DIN_PIN_SWAP_R::new(((self.bits >> 31) & 1) != 0)
86 }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91 f.debug_struct("MISC")
92 .field("cs0_dis", &format_args!("{}", self.cs0_dis().bit()))
93 .field("cs1_dis", &format_args!("{}", self.cs1_dis().bit()))
94 .field("cs2_dis", &format_args!("{}", self.cs2_dis().bit()))
95 .field("ck_dis", &format_args!("{}", self.ck_dis().bit()))
96 .field(
97 "master_cs_pol",
98 &format_args!("{}", self.master_cs_pol().bits()),
99 )
100 .field(
101 "slave_cs_pol",
102 &format_args!("{}", self.slave_cs_pol().bit()),
103 )
104 .field(
105 "ck_idle_edge",
106 &format_args!("{}", self.ck_idle_edge().bit()),
107 )
108 .field(
109 "cs_keep_active",
110 &format_args!("{}", self.cs_keep_active().bit()),
111 )
112 .field(
113 "quad_din_pin_swap",
114 &format_args!("{}", self.quad_din_pin_swap().bit()),
115 )
116 .finish()
117 }
118}
119#[cfg(feature = "impl-register-debug")]
120impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
121 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
122 core::fmt::Debug::fmt(&self.read(), f)
123 }
124}
125impl W {
126 #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
127 #[inline(always)]
128 #[must_use]
129 pub fn cs0_dis(&mut self) -> CS0_DIS_W<MISC_SPEC> {
130 CS0_DIS_W::new(self, 0)
131 }
132 #[doc = "Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."]
133 #[inline(always)]
134 #[must_use]
135 pub fn cs1_dis(&mut self) -> CS1_DIS_W<MISC_SPEC> {
136 CS1_DIS_W::new(self, 1)
137 }
138 #[doc = "Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."]
139 #[inline(always)]
140 #[must_use]
141 pub fn cs2_dis(&mut self) -> CS2_DIS_W<MISC_SPEC> {
142 CS2_DIS_W::new(self, 2)
143 }
144 #[doc = "Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
145 #[inline(always)]
146 #[must_use]
147 pub fn ck_dis(&mut self) -> CK_DIS_W<MISC_SPEC> {
148 CK_DIS_W::new(self, 6)
149 }
150 #[doc = "Bits 7:9 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."]
151 #[inline(always)]
152 #[must_use]
153 pub fn master_cs_pol(&mut self) -> MASTER_CS_POL_W<MISC_SPEC> {
154 MASTER_CS_POL_W::new(self, 7)
155 }
156 #[doc = "Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
157 #[inline(always)]
158 #[must_use]
159 pub fn slave_cs_pol(&mut self) -> SLAVE_CS_POL_W<MISC_SPEC> {
160 SLAVE_CS_POL_W::new(self, 23)
161 }
162 #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
163 #[inline(always)]
164 #[must_use]
165 pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<MISC_SPEC> {
166 CK_IDLE_EDGE_W::new(self, 29)
167 }
168 #[doc = "Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state."]
169 #[inline(always)]
170 #[must_use]
171 pub fn cs_keep_active(&mut self) -> CS_KEEP_ACTIVE_W<MISC_SPEC> {
172 CS_KEEP_ACTIVE_W::new(self, 30)
173 }
174 #[doc = "Bit 31 - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state."]
175 #[inline(always)]
176 #[must_use]
177 pub fn quad_din_pin_swap(&mut self) -> QUAD_DIN_PIN_SWAP_W<MISC_SPEC> {
178 QUAD_DIN_PIN_SWAP_W::new(self, 31)
179 }
180}
181#[doc = "SPI misc register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`misc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`misc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
182pub struct MISC_SPEC;
183impl crate::RegisterSpec for MISC_SPEC {
184 type Ux = u32;
185}
186#[doc = "`read()` method returns [`misc::R`](R) reader structure"]
187impl crate::Readable for MISC_SPEC {}
188#[doc = "`write(|w| ..)` method takes [`misc::W`](W) writer structure"]
189impl crate::Writable for MISC_SPEC {
190 type Safety = crate::Unsafe;
191 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
192 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
193}
194#[doc = "`reset()` method sets MISC to value 0x06"]
195impl crate::Resettable for MISC_SPEC {
196 const RESET_VALUE: u32 = 0x06;
197}