1#[doc = "Register `DIN_MODE` reader"]
2pub type R = crate::R<DIN_MODE_SPEC>;
3#[doc = "Register `DIN_MODE` writer"]
4pub type W = crate::W<DIN_MODE_SPEC>;
5#[doc = "Field `DIN0_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
6pub type DIN0_MODE_R = crate::FieldReader;
7#[doc = "Field `DIN0_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
8pub type DIN0_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `DIN1_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
10pub type DIN1_MODE_R = crate::FieldReader;
11#[doc = "Field `DIN1_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
12pub type DIN1_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `DIN2_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
14pub type DIN2_MODE_R = crate::FieldReader;
15#[doc = "Field `DIN2_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
16pub type DIN2_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `DIN3_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
18pub type DIN3_MODE_R = crate::FieldReader;
19#[doc = "Field `DIN3_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
20pub type DIN3_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `TIMING_HCLK_ACTIVE` reader - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."]
22pub type TIMING_HCLK_ACTIVE_R = crate::BitReader;
23#[doc = "Field `TIMING_HCLK_ACTIVE` writer - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."]
24pub type TIMING_HCLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26 #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
27 #[inline(always)]
28 pub fn din0_mode(&self) -> DIN0_MODE_R {
29 DIN0_MODE_R::new((self.bits & 3) as u8)
30 }
31 #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
32 #[inline(always)]
33 pub fn din1_mode(&self) -> DIN1_MODE_R {
34 DIN1_MODE_R::new(((self.bits >> 2) & 3) as u8)
35 }
36 #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
37 #[inline(always)]
38 pub fn din2_mode(&self) -> DIN2_MODE_R {
39 DIN2_MODE_R::new(((self.bits >> 4) & 3) as u8)
40 }
41 #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
42 #[inline(always)]
43 pub fn din3_mode(&self) -> DIN3_MODE_R {
44 DIN3_MODE_R::new(((self.bits >> 6) & 3) as u8)
45 }
46 #[doc = "Bit 16 - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."]
47 #[inline(always)]
48 pub fn timing_hclk_active(&self) -> TIMING_HCLK_ACTIVE_R {
49 TIMING_HCLK_ACTIVE_R::new(((self.bits >> 16) & 1) != 0)
50 }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55 f.debug_struct("DIN_MODE")
56 .field("din0_mode", &format_args!("{}", self.din0_mode().bits()))
57 .field("din1_mode", &format_args!("{}", self.din1_mode().bits()))
58 .field("din2_mode", &format_args!("{}", self.din2_mode().bits()))
59 .field("din3_mode", &format_args!("{}", self.din3_mode().bits()))
60 .field(
61 "timing_hclk_active",
62 &format_args!("{}", self.timing_hclk_active().bit()),
63 )
64 .finish()
65 }
66}
67#[cfg(feature = "impl-register-debug")]
68impl core::fmt::Debug for crate::generic::Reg<DIN_MODE_SPEC> {
69 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
70 core::fmt::Debug::fmt(&self.read(), f)
71 }
72}
73impl W {
74 #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
75 #[inline(always)]
76 #[must_use]
77 pub fn din0_mode(&mut self) -> DIN0_MODE_W<DIN_MODE_SPEC> {
78 DIN0_MODE_W::new(self, 0)
79 }
80 #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
81 #[inline(always)]
82 #[must_use]
83 pub fn din1_mode(&mut self) -> DIN1_MODE_W<DIN_MODE_SPEC> {
84 DIN1_MODE_W::new(self, 2)
85 }
86 #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
87 #[inline(always)]
88 #[must_use]
89 pub fn din2_mode(&mut self) -> DIN2_MODE_W<DIN_MODE_SPEC> {
90 DIN2_MODE_W::new(self, 4)
91 }
92 #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
93 #[inline(always)]
94 #[must_use]
95 pub fn din3_mode(&mut self) -> DIN3_MODE_W<DIN_MODE_SPEC> {
96 DIN3_MODE_W::new(self, 6)
97 }
98 #[doc = "Bit 16 - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."]
99 #[inline(always)]
100 #[must_use]
101 pub fn timing_hclk_active(&mut self) -> TIMING_HCLK_ACTIVE_W<DIN_MODE_SPEC> {
102 TIMING_HCLK_ACTIVE_W::new(self, 16)
103 }
104}
105#[doc = "SPI input delay mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`din_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
106pub struct DIN_MODE_SPEC;
107impl crate::RegisterSpec for DIN_MODE_SPEC {
108 type Ux = u32;
109}
110#[doc = "`read()` method returns [`din_mode::R`](R) reader structure"]
111impl crate::Readable for DIN_MODE_SPEC {}
112#[doc = "`write(|w| ..)` method takes [`din_mode::W`](W) writer structure"]
113impl crate::Writable for DIN_MODE_SPEC {
114 type Safety = crate::Unsafe;
115 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
116 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117}
118#[doc = "`reset()` method sets DIN_MODE to value 0"]
119impl crate::Resettable for DIN_MODE_SPEC {
120 const RESET_VALUE: u32 = 0;
121}