esp32p4/spi1/
sus_status.rs1#[doc = "Register `SUS_STATUS` reader"]
2pub type R = crate::R<SUS_STATUS_SPEC>;
3#[doc = "Register `SUS_STATUS` writer"]
4pub type W = crate::W<SUS_STATUS_SPEC>;
5#[doc = "Field `FLASH_SUS` reader - The status of flash suspend, only used in SPI1."]
6pub type FLASH_SUS_R = crate::BitReader;
7#[doc = "Field `FLASH_SUS` writer - The status of flash suspend, only used in SPI1."]
8pub type FLASH_SUS_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `WAIT_PESR_CMD_2B` reader - 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[15:0\\] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[7:0\\] to check SUS/SUS1/SUS2 bit."]
10pub type WAIT_PESR_CMD_2B_R = crate::BitReader;
11#[doc = "Field `WAIT_PESR_CMD_2B` writer - 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[15:0\\] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[7:0\\] to check SUS/SUS1/SUS2 bit."]
12pub type WAIT_PESR_CMD_2B_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FLASH_HPM_DLY_128` reader - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after HPM command is sent."]
14pub type FLASH_HPM_DLY_128_R = crate::BitReader;
15#[doc = "Field `FLASH_HPM_DLY_128` writer - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after HPM command is sent."]
16pub type FLASH_HPM_DLY_128_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FLASH_RES_DLY_128` reader - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after RES command is sent."]
18pub type FLASH_RES_DLY_128_R = crate::BitReader;
19#[doc = "Field `FLASH_RES_DLY_128` writer - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after RES command is sent."]
20pub type FLASH_RES_DLY_128_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FLASH_DP_DLY_128` reader - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after DP command is sent."]
22pub type FLASH_DP_DLY_128_R = crate::BitReader;
23#[doc = "Field `FLASH_DP_DLY_128` writer - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after DP command is sent."]
24pub type FLASH_DP_DLY_128_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FLASH_PER_DLY_128` reader - Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PER command is sent."]
26pub type FLASH_PER_DLY_128_R = crate::BitReader;
27#[doc = "Field `FLASH_PER_DLY_128` writer - Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PER command is sent."]
28pub type FLASH_PER_DLY_128_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FLASH_PES_DLY_128` reader - Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PES command is sent."]
30pub type FLASH_PES_DLY_128_R = crate::BitReader;
31#[doc = "Field `FLASH_PES_DLY_128` writer - Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PES command is sent."]
32pub type FLASH_PES_DLY_128_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SPI0_LOCK_EN` reader - 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it."]
34pub type SPI0_LOCK_EN_R = crate::BitReader;
35#[doc = "Field `SPI0_LOCK_EN` writer - 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it."]
36pub type SPI0_LOCK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `FLASH_PESR_CMD_2B` reader - 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8."]
38pub type FLASH_PESR_CMD_2B_R = crate::BitReader;
39#[doc = "Field `FLASH_PESR_CMD_2B` writer - 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8."]
40pub type FLASH_PESR_CMD_2B_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `FLASH_PER_COMMAND` reader - Program/Erase resume command."]
42pub type FLASH_PER_COMMAND_R = crate::FieldReader<u16>;
43#[doc = "Field `FLASH_PER_COMMAND` writer - Program/Erase resume command."]
44pub type FLASH_PER_COMMAND_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
45impl R {
46 #[doc = "Bit 0 - The status of flash suspend, only used in SPI1."]
47 #[inline(always)]
48 pub fn flash_sus(&self) -> FLASH_SUS_R {
49 FLASH_SUS_R::new((self.bits & 1) != 0)
50 }
51 #[doc = "Bit 1 - 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[15:0\\] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[7:0\\] to check SUS/SUS1/SUS2 bit."]
52 #[inline(always)]
53 pub fn wait_pesr_cmd_2b(&self) -> WAIT_PESR_CMD_2B_R {
54 WAIT_PESR_CMD_2B_R::new(((self.bits >> 1) & 1) != 0)
55 }
56 #[doc = "Bit 2 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after HPM command is sent."]
57 #[inline(always)]
58 pub fn flash_hpm_dly_128(&self) -> FLASH_HPM_DLY_128_R {
59 FLASH_HPM_DLY_128_R::new(((self.bits >> 2) & 1) != 0)
60 }
61 #[doc = "Bit 3 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after RES command is sent."]
62 #[inline(always)]
63 pub fn flash_res_dly_128(&self) -> FLASH_RES_DLY_128_R {
64 FLASH_RES_DLY_128_R::new(((self.bits >> 3) & 1) != 0)
65 }
66 #[doc = "Bit 4 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after DP command is sent."]
67 #[inline(always)]
68 pub fn flash_dp_dly_128(&self) -> FLASH_DP_DLY_128_R {
69 FLASH_DP_DLY_128_R::new(((self.bits >> 4) & 1) != 0)
70 }
71 #[doc = "Bit 5 - Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PER command is sent."]
72 #[inline(always)]
73 pub fn flash_per_dly_128(&self) -> FLASH_PER_DLY_128_R {
74 FLASH_PER_DLY_128_R::new(((self.bits >> 5) & 1) != 0)
75 }
76 #[doc = "Bit 6 - Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PES command is sent."]
77 #[inline(always)]
78 pub fn flash_pes_dly_128(&self) -> FLASH_PES_DLY_128_R {
79 FLASH_PES_DLY_128_R::new(((self.bits >> 6) & 1) != 0)
80 }
81 #[doc = "Bit 7 - 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it."]
82 #[inline(always)]
83 pub fn spi0_lock_en(&self) -> SPI0_LOCK_EN_R {
84 SPI0_LOCK_EN_R::new(((self.bits >> 7) & 1) != 0)
85 }
86 #[doc = "Bit 15 - 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8."]
87 #[inline(always)]
88 pub fn flash_pesr_cmd_2b(&self) -> FLASH_PESR_CMD_2B_R {
89 FLASH_PESR_CMD_2B_R::new(((self.bits >> 15) & 1) != 0)
90 }
91 #[doc = "Bits 16:31 - Program/Erase resume command."]
92 #[inline(always)]
93 pub fn flash_per_command(&self) -> FLASH_PER_COMMAND_R {
94 FLASH_PER_COMMAND_R::new(((self.bits >> 16) & 0xffff) as u16)
95 }
96}
97#[cfg(feature = "impl-register-debug")]
98impl core::fmt::Debug for R {
99 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
100 f.debug_struct("SUS_STATUS")
101 .field("flash_sus", &format_args!("{}", self.flash_sus().bit()))
102 .field(
103 "wait_pesr_cmd_2b",
104 &format_args!("{}", self.wait_pesr_cmd_2b().bit()),
105 )
106 .field(
107 "flash_hpm_dly_128",
108 &format_args!("{}", self.flash_hpm_dly_128().bit()),
109 )
110 .field(
111 "flash_res_dly_128",
112 &format_args!("{}", self.flash_res_dly_128().bit()),
113 )
114 .field(
115 "flash_dp_dly_128",
116 &format_args!("{}", self.flash_dp_dly_128().bit()),
117 )
118 .field(
119 "flash_per_dly_128",
120 &format_args!("{}", self.flash_per_dly_128().bit()),
121 )
122 .field(
123 "flash_pes_dly_128",
124 &format_args!("{}", self.flash_pes_dly_128().bit()),
125 )
126 .field(
127 "spi0_lock_en",
128 &format_args!("{}", self.spi0_lock_en().bit()),
129 )
130 .field(
131 "flash_pesr_cmd_2b",
132 &format_args!("{}", self.flash_pesr_cmd_2b().bit()),
133 )
134 .field(
135 "flash_per_command",
136 &format_args!("{}", self.flash_per_command().bits()),
137 )
138 .finish()
139 }
140}
141#[cfg(feature = "impl-register-debug")]
142impl core::fmt::Debug for crate::generic::Reg<SUS_STATUS_SPEC> {
143 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
144 core::fmt::Debug::fmt(&self.read(), f)
145 }
146}
147impl W {
148 #[doc = "Bit 0 - The status of flash suspend, only used in SPI1."]
149 #[inline(always)]
150 #[must_use]
151 pub fn flash_sus(&mut self) -> FLASH_SUS_W<SUS_STATUS_SPEC> {
152 FLASH_SUS_W::new(self, 0)
153 }
154 #[doc = "Bit 1 - 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[15:0\\] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[7:0\\] to check SUS/SUS1/SUS2 bit."]
155 #[inline(always)]
156 #[must_use]
157 pub fn wait_pesr_cmd_2b(&mut self) -> WAIT_PESR_CMD_2B_W<SUS_STATUS_SPEC> {
158 WAIT_PESR_CMD_2B_W::new(self, 1)
159 }
160 #[doc = "Bit 2 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after HPM command is sent."]
161 #[inline(always)]
162 #[must_use]
163 pub fn flash_hpm_dly_128(&mut self) -> FLASH_HPM_DLY_128_W<SUS_STATUS_SPEC> {
164 FLASH_HPM_DLY_128_W::new(self, 2)
165 }
166 #[doc = "Bit 3 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after RES command is sent."]
167 #[inline(always)]
168 #[must_use]
169 pub fn flash_res_dly_128(&mut self) -> FLASH_RES_DLY_128_W<SUS_STATUS_SPEC> {
170 FLASH_RES_DLY_128_W::new(self, 3)
171 }
172 #[doc = "Bit 4 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after DP command is sent."]
173 #[inline(always)]
174 #[must_use]
175 pub fn flash_dp_dly_128(&mut self) -> FLASH_DP_DLY_128_W<SUS_STATUS_SPEC> {
176 FLASH_DP_DLY_128_W::new(self, 4)
177 }
178 #[doc = "Bit 5 - Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PER command is sent."]
179 #[inline(always)]
180 #[must_use]
181 pub fn flash_per_dly_128(&mut self) -> FLASH_PER_DLY_128_W<SUS_STATUS_SPEC> {
182 FLASH_PER_DLY_128_W::new(self, 5)
183 }
184 #[doc = "Bit 6 - Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PES command is sent."]
185 #[inline(always)]
186 #[must_use]
187 pub fn flash_pes_dly_128(&mut self) -> FLASH_PES_DLY_128_W<SUS_STATUS_SPEC> {
188 FLASH_PES_DLY_128_W::new(self, 6)
189 }
190 #[doc = "Bit 7 - 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it."]
191 #[inline(always)]
192 #[must_use]
193 pub fn spi0_lock_en(&mut self) -> SPI0_LOCK_EN_W<SUS_STATUS_SPEC> {
194 SPI0_LOCK_EN_W::new(self, 7)
195 }
196 #[doc = "Bit 15 - 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8."]
197 #[inline(always)]
198 #[must_use]
199 pub fn flash_pesr_cmd_2b(&mut self) -> FLASH_PESR_CMD_2B_W<SUS_STATUS_SPEC> {
200 FLASH_PESR_CMD_2B_W::new(self, 15)
201 }
202 #[doc = "Bits 16:31 - Program/Erase resume command."]
203 #[inline(always)]
204 #[must_use]
205 pub fn flash_per_command(&mut self) -> FLASH_PER_COMMAND_W<SUS_STATUS_SPEC> {
206 FLASH_PER_COMMAND_W::new(self, 16)
207 }
208}
209#[doc = "SPI1 flash suspend status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sus_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sus_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
210pub struct SUS_STATUS_SPEC;
211impl crate::RegisterSpec for SUS_STATUS_SPEC {
212 type Ux = u32;
213}
214#[doc = "`read()` method returns [`sus_status::R`](R) reader structure"]
215impl crate::Readable for SUS_STATUS_SPEC {}
216#[doc = "`write(|w| ..)` method takes [`sus_status::W`](W) writer structure"]
217impl crate::Writable for SUS_STATUS_SPEC {
218 type Safety = crate::Unsafe;
219 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
220 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
221}
222#[doc = "`reset()` method sets SUS_STATUS to value 0x7a7a_0000"]
223impl crate::Resettable for SUS_STATUS_SPEC {
224 const RESET_VALUE: u32 = 0x7a7a_0000;
225}