1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `PER_END` reader - The enable bit for SPI_MEM_PER_END_INT interrupt."]
6pub type PER_END_R = crate::BitReader;
7#[doc = "Field `PER_END` writer - The enable bit for SPI_MEM_PER_END_INT interrupt."]
8pub type PER_END_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PES_END` reader - The enable bit for SPI_MEM_PES_END_INT interrupt."]
10pub type PES_END_R = crate::BitReader;
11#[doc = "Field `PES_END` writer - The enable bit for SPI_MEM_PES_END_INT interrupt."]
12pub type PES_END_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `WPE_END` reader - The enable bit for SPI_MEM_WPE_END_INT interrupt."]
14pub type WPE_END_R = crate::BitReader;
15#[doc = "Field `WPE_END` writer - The enable bit for SPI_MEM_WPE_END_INT interrupt."]
16pub type WPE_END_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SLV_ST_END` reader - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."]
18pub type SLV_ST_END_R = crate::BitReader;
19#[doc = "Field `SLV_ST_END` writer - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."]
20pub type SLV_ST_END_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `MST_ST_END` reader - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."]
22pub type MST_ST_END_R = crate::BitReader;
23#[doc = "Field `MST_ST_END` writer - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."]
24pub type MST_ST_END_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `BROWN_OUT` reader - The enable bit for SPI_MEM_BROWN_OUT_INT interrupt."]
26pub type BROWN_OUT_R = crate::BitReader;
27#[doc = "Field `BROWN_OUT` writer - The enable bit for SPI_MEM_BROWN_OUT_INT interrupt."]
28pub type BROWN_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30 #[doc = "Bit 0 - The enable bit for SPI_MEM_PER_END_INT interrupt."]
31 #[inline(always)]
32 pub fn per_end(&self) -> PER_END_R {
33 PER_END_R::new((self.bits & 1) != 0)
34 }
35 #[doc = "Bit 1 - The enable bit for SPI_MEM_PES_END_INT interrupt."]
36 #[inline(always)]
37 pub fn pes_end(&self) -> PES_END_R {
38 PES_END_R::new(((self.bits >> 1) & 1) != 0)
39 }
40 #[doc = "Bit 2 - The enable bit for SPI_MEM_WPE_END_INT interrupt."]
41 #[inline(always)]
42 pub fn wpe_end(&self) -> WPE_END_R {
43 WPE_END_R::new(((self.bits >> 2) & 1) != 0)
44 }
45 #[doc = "Bit 3 - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."]
46 #[inline(always)]
47 pub fn slv_st_end(&self) -> SLV_ST_END_R {
48 SLV_ST_END_R::new(((self.bits >> 3) & 1) != 0)
49 }
50 #[doc = "Bit 4 - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."]
51 #[inline(always)]
52 pub fn mst_st_end(&self) -> MST_ST_END_R {
53 MST_ST_END_R::new(((self.bits >> 4) & 1) != 0)
54 }
55 #[doc = "Bit 10 - The enable bit for SPI_MEM_BROWN_OUT_INT interrupt."]
56 #[inline(always)]
57 pub fn brown_out(&self) -> BROWN_OUT_R {
58 BROWN_OUT_R::new(((self.bits >> 10) & 1) != 0)
59 }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64 f.debug_struct("INT_ENA")
65 .field("per_end", &format_args!("{}", self.per_end().bit()))
66 .field("pes_end", &format_args!("{}", self.pes_end().bit()))
67 .field("wpe_end", &format_args!("{}", self.wpe_end().bit()))
68 .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
69 .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
70 .field("brown_out", &format_args!("{}", self.brown_out().bit()))
71 .finish()
72 }
73}
74#[cfg(feature = "impl-register-debug")]
75impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
76 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
77 core::fmt::Debug::fmt(&self.read(), f)
78 }
79}
80impl W {
81 #[doc = "Bit 0 - The enable bit for SPI_MEM_PER_END_INT interrupt."]
82 #[inline(always)]
83 #[must_use]
84 pub fn per_end(&mut self) -> PER_END_W<INT_ENA_SPEC> {
85 PER_END_W::new(self, 0)
86 }
87 #[doc = "Bit 1 - The enable bit for SPI_MEM_PES_END_INT interrupt."]
88 #[inline(always)]
89 #[must_use]
90 pub fn pes_end(&mut self) -> PES_END_W<INT_ENA_SPEC> {
91 PES_END_W::new(self, 1)
92 }
93 #[doc = "Bit 2 - The enable bit for SPI_MEM_WPE_END_INT interrupt."]
94 #[inline(always)]
95 #[must_use]
96 pub fn wpe_end(&mut self) -> WPE_END_W<INT_ENA_SPEC> {
97 WPE_END_W::new(self, 2)
98 }
99 #[doc = "Bit 3 - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."]
100 #[inline(always)]
101 #[must_use]
102 pub fn slv_st_end(&mut self) -> SLV_ST_END_W<INT_ENA_SPEC> {
103 SLV_ST_END_W::new(self, 3)
104 }
105 #[doc = "Bit 4 - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."]
106 #[inline(always)]
107 #[must_use]
108 pub fn mst_st_end(&mut self) -> MST_ST_END_W<INT_ENA_SPEC> {
109 MST_ST_END_W::new(self, 4)
110 }
111 #[doc = "Bit 10 - The enable bit for SPI_MEM_BROWN_OUT_INT interrupt."]
112 #[inline(always)]
113 #[must_use]
114 pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_ENA_SPEC> {
115 BROWN_OUT_W::new(self, 10)
116 }
117}
118#[doc = "SPI1 interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
119pub struct INT_ENA_SPEC;
120impl crate::RegisterSpec for INT_ENA_SPEC {
121 type Ux = u32;
122}
123#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
124impl crate::Readable for INT_ENA_SPEC {}
125#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
126impl crate::Writable for INT_ENA_SPEC {
127 type Safety = crate::Unsafe;
128 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
129 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
130}
131#[doc = "`reset()` method sets INT_ENA to value 0"]
132impl crate::Resettable for INT_ENA_SPEC {
133 const RESET_VALUE: u32 = 0;
134}