1#[doc = "Register `FLASH_SUS_CTRL` reader"]
2pub type R = crate::R<FLASH_SUS_CTRL_SPEC>;
3#[doc = "Register `FLASH_SUS_CTRL` writer"]
4pub type W = crate::W<FLASH_SUS_CTRL_SPEC>;
5#[doc = "Field `FLASH_PER` reader - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
6pub type FLASH_PER_R = crate::BitReader;
7#[doc = "Field `FLASH_PER` writer - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
8pub type FLASH_PER_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FLASH_PES` reader - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
10pub type FLASH_PES_R = crate::BitReader;
11#[doc = "Field `FLASH_PES` writer - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
12pub type FLASH_PES_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FLASH_PER_WAIT_EN` reader - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent."]
14pub type FLASH_PER_WAIT_EN_R = crate::BitReader;
15#[doc = "Field `FLASH_PER_WAIT_EN` writer - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent."]
16pub type FLASH_PER_WAIT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FLASH_PES_WAIT_EN` reader - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent."]
18pub type FLASH_PES_WAIT_EN_R = crate::BitReader;
19#[doc = "Field `FLASH_PES_WAIT_EN` writer - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent."]
20pub type FLASH_PES_WAIT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `PES_PER_EN` reader - Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done."]
22pub type PES_PER_EN_R = crate::BitReader;
23#[doc = "Field `PES_PER_EN` writer - Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done."]
24pub type PES_PER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FLASH_PES_EN` reader - Set this bit to enable Auto-suspending function."]
26pub type FLASH_PES_EN_R = crate::BitReader;
27#[doc = "Field `FLASH_PES_EN` writer - Set this bit to enable Auto-suspending function."]
28pub type FLASH_PES_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `PESR_END_MSK` reader - The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in\\[15:0\\](only status_in\\[7:0\\] is valid when only one byte of data is read out, status_in\\[15:0\\] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in\\[15:0\\]^ SPI_MEM_PESR_END_MSK\\[15:0\\]."]
30pub type PESR_END_MSK_R = crate::FieldReader<u16>;
31#[doc = "Field `PESR_END_MSK` writer - The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in\\[15:0\\](only status_in\\[7:0\\] is valid when only one byte of data is read out, status_in\\[15:0\\] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in\\[15:0\\]^ SPI_MEM_PESR_END_MSK\\[15:0\\]."]
32pub type PESR_END_MSK_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
33#[doc = "Field `SPI_FMEM_RD_SUS_2B` reader - 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit"]
34pub type SPI_FMEM_RD_SUS_2B_R = crate::BitReader;
35#[doc = "Field `SPI_FMEM_RD_SUS_2B` writer - 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit"]
36pub type SPI_FMEM_RD_SUS_2B_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `PER_END_EN` reader - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0."]
38pub type PER_END_EN_R = crate::BitReader;
39#[doc = "Field `PER_END_EN` writer - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0."]
40pub type PER_END_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `PES_END_EN` reader - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0."]
42pub type PES_END_EN_R = crate::BitReader;
43#[doc = "Field `PES_END_EN` writer - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0."]
44pub type PES_END_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SUS_TIMEOUT_CNT` reader - When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT\\[6:0\\] times, it will be treated as check pass."]
46pub type SUS_TIMEOUT_CNT_R = crate::FieldReader;
47#[doc = "Field `SUS_TIMEOUT_CNT` writer - When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT\\[6:0\\] times, it will be treated as check pass."]
48pub type SUS_TIMEOUT_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
49impl R {
50 #[doc = "Bit 0 - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
51 #[inline(always)]
52 pub fn flash_per(&self) -> FLASH_PER_R {
53 FLASH_PER_R::new((self.bits & 1) != 0)
54 }
55 #[doc = "Bit 1 - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
56 #[inline(always)]
57 pub fn flash_pes(&self) -> FLASH_PES_R {
58 FLASH_PES_R::new(((self.bits >> 1) & 1) != 0)
59 }
60 #[doc = "Bit 2 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent."]
61 #[inline(always)]
62 pub fn flash_per_wait_en(&self) -> FLASH_PER_WAIT_EN_R {
63 FLASH_PER_WAIT_EN_R::new(((self.bits >> 2) & 1) != 0)
64 }
65 #[doc = "Bit 3 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent."]
66 #[inline(always)]
67 pub fn flash_pes_wait_en(&self) -> FLASH_PES_WAIT_EN_R {
68 FLASH_PES_WAIT_EN_R::new(((self.bits >> 3) & 1) != 0)
69 }
70 #[doc = "Bit 4 - Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done."]
71 #[inline(always)]
72 pub fn pes_per_en(&self) -> PES_PER_EN_R {
73 PES_PER_EN_R::new(((self.bits >> 4) & 1) != 0)
74 }
75 #[doc = "Bit 5 - Set this bit to enable Auto-suspending function."]
76 #[inline(always)]
77 pub fn flash_pes_en(&self) -> FLASH_PES_EN_R {
78 FLASH_PES_EN_R::new(((self.bits >> 5) & 1) != 0)
79 }
80 #[doc = "Bits 6:21 - The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in\\[15:0\\](only status_in\\[7:0\\] is valid when only one byte of data is read out, status_in\\[15:0\\] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in\\[15:0\\]^ SPI_MEM_PESR_END_MSK\\[15:0\\]."]
81 #[inline(always)]
82 pub fn pesr_end_msk(&self) -> PESR_END_MSK_R {
83 PESR_END_MSK_R::new(((self.bits >> 6) & 0xffff) as u16)
84 }
85 #[doc = "Bit 22 - 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit"]
86 #[inline(always)]
87 pub fn spi_fmem_rd_sus_2b(&self) -> SPI_FMEM_RD_SUS_2B_R {
88 SPI_FMEM_RD_SUS_2B_R::new(((self.bits >> 22) & 1) != 0)
89 }
90 #[doc = "Bit 23 - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0."]
91 #[inline(always)]
92 pub fn per_end_en(&self) -> PER_END_EN_R {
93 PER_END_EN_R::new(((self.bits >> 23) & 1) != 0)
94 }
95 #[doc = "Bit 24 - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0."]
96 #[inline(always)]
97 pub fn pes_end_en(&self) -> PES_END_EN_R {
98 PES_END_EN_R::new(((self.bits >> 24) & 1) != 0)
99 }
100 #[doc = "Bits 25:31 - When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT\\[6:0\\] times, it will be treated as check pass."]
101 #[inline(always)]
102 pub fn sus_timeout_cnt(&self) -> SUS_TIMEOUT_CNT_R {
103 SUS_TIMEOUT_CNT_R::new(((self.bits >> 25) & 0x7f) as u8)
104 }
105}
106#[cfg(feature = "impl-register-debug")]
107impl core::fmt::Debug for R {
108 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
109 f.debug_struct("FLASH_SUS_CTRL")
110 .field("flash_per", &format_args!("{}", self.flash_per().bit()))
111 .field("flash_pes", &format_args!("{}", self.flash_pes().bit()))
112 .field(
113 "flash_per_wait_en",
114 &format_args!("{}", self.flash_per_wait_en().bit()),
115 )
116 .field(
117 "flash_pes_wait_en",
118 &format_args!("{}", self.flash_pes_wait_en().bit()),
119 )
120 .field("pes_per_en", &format_args!("{}", self.pes_per_en().bit()))
121 .field(
122 "flash_pes_en",
123 &format_args!("{}", self.flash_pes_en().bit()),
124 )
125 .field(
126 "pesr_end_msk",
127 &format_args!("{}", self.pesr_end_msk().bits()),
128 )
129 .field(
130 "spi_fmem_rd_sus_2b",
131 &format_args!("{}", self.spi_fmem_rd_sus_2b().bit()),
132 )
133 .field("per_end_en", &format_args!("{}", self.per_end_en().bit()))
134 .field("pes_end_en", &format_args!("{}", self.pes_end_en().bit()))
135 .field(
136 "sus_timeout_cnt",
137 &format_args!("{}", self.sus_timeout_cnt().bits()),
138 )
139 .finish()
140 }
141}
142#[cfg(feature = "impl-register-debug")]
143impl core::fmt::Debug for crate::generic::Reg<FLASH_SUS_CTRL_SPEC> {
144 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
145 core::fmt::Debug::fmt(&self.read(), f)
146 }
147}
148impl W {
149 #[doc = "Bit 0 - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
150 #[inline(always)]
151 #[must_use]
152 pub fn flash_per(&mut self) -> FLASH_PER_W<FLASH_SUS_CTRL_SPEC> {
153 FLASH_PER_W::new(self, 0)
154 }
155 #[doc = "Bit 1 - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
156 #[inline(always)]
157 #[must_use]
158 pub fn flash_pes(&mut self) -> FLASH_PES_W<FLASH_SUS_CTRL_SPEC> {
159 FLASH_PES_W::new(self, 1)
160 }
161 #[doc = "Bit 2 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent."]
162 #[inline(always)]
163 #[must_use]
164 pub fn flash_per_wait_en(&mut self) -> FLASH_PER_WAIT_EN_W<FLASH_SUS_CTRL_SPEC> {
165 FLASH_PER_WAIT_EN_W::new(self, 2)
166 }
167 #[doc = "Bit 3 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent."]
168 #[inline(always)]
169 #[must_use]
170 pub fn flash_pes_wait_en(&mut self) -> FLASH_PES_WAIT_EN_W<FLASH_SUS_CTRL_SPEC> {
171 FLASH_PES_WAIT_EN_W::new(self, 3)
172 }
173 #[doc = "Bit 4 - Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done."]
174 #[inline(always)]
175 #[must_use]
176 pub fn pes_per_en(&mut self) -> PES_PER_EN_W<FLASH_SUS_CTRL_SPEC> {
177 PES_PER_EN_W::new(self, 4)
178 }
179 #[doc = "Bit 5 - Set this bit to enable Auto-suspending function."]
180 #[inline(always)]
181 #[must_use]
182 pub fn flash_pes_en(&mut self) -> FLASH_PES_EN_W<FLASH_SUS_CTRL_SPEC> {
183 FLASH_PES_EN_W::new(self, 5)
184 }
185 #[doc = "Bits 6:21 - The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in\\[15:0\\](only status_in\\[7:0\\] is valid when only one byte of data is read out, status_in\\[15:0\\] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in\\[15:0\\]^ SPI_MEM_PESR_END_MSK\\[15:0\\]."]
186 #[inline(always)]
187 #[must_use]
188 pub fn pesr_end_msk(&mut self) -> PESR_END_MSK_W<FLASH_SUS_CTRL_SPEC> {
189 PESR_END_MSK_W::new(self, 6)
190 }
191 #[doc = "Bit 22 - 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit"]
192 #[inline(always)]
193 #[must_use]
194 pub fn spi_fmem_rd_sus_2b(&mut self) -> SPI_FMEM_RD_SUS_2B_W<FLASH_SUS_CTRL_SPEC> {
195 SPI_FMEM_RD_SUS_2B_W::new(self, 22)
196 }
197 #[doc = "Bit 23 - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0."]
198 #[inline(always)]
199 #[must_use]
200 pub fn per_end_en(&mut self) -> PER_END_EN_W<FLASH_SUS_CTRL_SPEC> {
201 PER_END_EN_W::new(self, 23)
202 }
203 #[doc = "Bit 24 - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0."]
204 #[inline(always)]
205 #[must_use]
206 pub fn pes_end_en(&mut self) -> PES_END_EN_W<FLASH_SUS_CTRL_SPEC> {
207 PES_END_EN_W::new(self, 24)
208 }
209 #[doc = "Bits 25:31 - When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT\\[6:0\\] times, it will be treated as check pass."]
210 #[inline(always)]
211 #[must_use]
212 pub fn sus_timeout_cnt(&mut self) -> SUS_TIMEOUT_CNT_W<FLASH_SUS_CTRL_SPEC> {
213 SUS_TIMEOUT_CNT_W::new(self, 25)
214 }
215}
216#[doc = "SPI1 flash suspend control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`flash_sus_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flash_sus_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
217pub struct FLASH_SUS_CTRL_SPEC;
218impl crate::RegisterSpec for FLASH_SUS_CTRL_SPEC {
219 type Ux = u32;
220}
221#[doc = "`read()` method returns [`flash_sus_ctrl::R`](R) reader structure"]
222impl crate::Readable for FLASH_SUS_CTRL_SPEC {}
223#[doc = "`write(|w| ..)` method takes [`flash_sus_ctrl::W`](W) writer structure"]
224impl crate::Writable for FLASH_SUS_CTRL_SPEC {
225 type Safety = crate::Unsafe;
226 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
227 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
228}
229#[doc = "`reset()` method sets FLASH_SUS_CTRL to value 0x0800_2000"]
230impl crate::Resettable for FLASH_SUS_CTRL_SPEC {
231 const RESET_VALUE: u32 = 0x0800_2000;
232}