1#[doc = "Register `USER1` reader"]
2pub type R = crate::R<USER1_SPEC>;
3#[doc = "Register `USER1` writer"]
4pub type W = crate::W<USER1_SPEC>;
5#[doc = "Field `USR_DUMMY_CYCLELEN` reader - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
6pub type USR_DUMMY_CYCLELEN_R = crate::FieldReader;
7#[doc = "Field `USR_DUMMY_CYCLELEN` writer - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
8pub type USR_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `USR_DBYTELEN` reader - SPI0 USR_CMD read or write data byte length -1"]
10pub type USR_DBYTELEN_R = crate::FieldReader;
11#[doc = "Field `USR_ADDR_BITLEN` reader - The length in bits of address phase. The register value shall be (bit_num-1)."]
12pub type USR_ADDR_BITLEN_R = crate::FieldReader;
13#[doc = "Field `USR_ADDR_BITLEN` writer - The length in bits of address phase. The register value shall be (bit_num-1)."]
14pub type USR_ADDR_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
15impl R {
16 #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
17 #[inline(always)]
18 pub fn usr_dummy_cyclelen(&self) -> USR_DUMMY_CYCLELEN_R {
19 USR_DUMMY_CYCLELEN_R::new((self.bits & 0x3f) as u8)
20 }
21 #[doc = "Bits 6:8 - SPI0 USR_CMD read or write data byte length -1"]
22 #[inline(always)]
23 pub fn usr_dbytelen(&self) -> USR_DBYTELEN_R {
24 USR_DBYTELEN_R::new(((self.bits >> 6) & 7) as u8)
25 }
26 #[doc = "Bits 26:31 - The length in bits of address phase. The register value shall be (bit_num-1)."]
27 #[inline(always)]
28 pub fn usr_addr_bitlen(&self) -> USR_ADDR_BITLEN_R {
29 USR_ADDR_BITLEN_R::new(((self.bits >> 26) & 0x3f) as u8)
30 }
31}
32#[cfg(feature = "impl-register-debug")]
33impl core::fmt::Debug for R {
34 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
35 f.debug_struct("USER1")
36 .field(
37 "usr_dummy_cyclelen",
38 &format_args!("{}", self.usr_dummy_cyclelen().bits()),
39 )
40 .field(
41 "usr_dbytelen",
42 &format_args!("{}", self.usr_dbytelen().bits()),
43 )
44 .field(
45 "usr_addr_bitlen",
46 &format_args!("{}", self.usr_addr_bitlen().bits()),
47 )
48 .finish()
49 }
50}
51#[cfg(feature = "impl-register-debug")]
52impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
53 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
54 core::fmt::Debug::fmt(&self.read(), f)
55 }
56}
57impl W {
58 #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
59 #[inline(always)]
60 #[must_use]
61 pub fn usr_dummy_cyclelen(&mut self) -> USR_DUMMY_CYCLELEN_W<USER1_SPEC> {
62 USR_DUMMY_CYCLELEN_W::new(self, 0)
63 }
64 #[doc = "Bits 26:31 - The length in bits of address phase. The register value shall be (bit_num-1)."]
65 #[inline(always)]
66 #[must_use]
67 pub fn usr_addr_bitlen(&mut self) -> USR_ADDR_BITLEN_W<USER1_SPEC> {
68 USR_ADDR_BITLEN_W::new(self, 26)
69 }
70}
71#[doc = "SPI0 user1 register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`user1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`user1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
72pub struct USER1_SPEC;
73impl crate::RegisterSpec for USER1_SPEC {
74 type Ux = u32;
75}
76#[doc = "`read()` method returns [`user1::R`](R) reader structure"]
77impl crate::Readable for USER1_SPEC {}
78#[doc = "`write(|w| ..)` method takes [`user1::W`](W) writer structure"]
79impl crate::Writable for USER1_SPEC {
80 type Safety = crate::Unsafe;
81 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
82 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
83}
84#[doc = "`reset()` method sets USER1 to value 0x5c00_0047"]
85impl crate::Resettable for USER1_SPEC {
86 const RESET_VALUE: u32 = 0x5c00_0047;
87}