1#[doc = "Register `SPI_SMEM_DIN_NUM` reader"]
2pub type R = crate::R<SPI_SMEM_DIN_NUM_SPEC>;
3#[doc = "Register `SPI_SMEM_DIN_NUM` writer"]
4pub type W = crate::W<SPI_SMEM_DIN_NUM_SPEC>;
5#[doc = "Field `SPI_SMEM_DIN0_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
6pub type SPI_SMEM_DIN0_NUM_R = crate::FieldReader;
7#[doc = "Field `SPI_SMEM_DIN0_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
8pub type SPI_SMEM_DIN0_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `SPI_SMEM_DIN1_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
10pub type SPI_SMEM_DIN1_NUM_R = crate::FieldReader;
11#[doc = "Field `SPI_SMEM_DIN1_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
12pub type SPI_SMEM_DIN1_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `SPI_SMEM_DIN2_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
14pub type SPI_SMEM_DIN2_NUM_R = crate::FieldReader;
15#[doc = "Field `SPI_SMEM_DIN2_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
16pub type SPI_SMEM_DIN2_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `SPI_SMEM_DIN3_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
18pub type SPI_SMEM_DIN3_NUM_R = crate::FieldReader;
19#[doc = "Field `SPI_SMEM_DIN3_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
20pub type SPI_SMEM_DIN3_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `SPI_SMEM_DIN4_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
22pub type SPI_SMEM_DIN4_NUM_R = crate::FieldReader;
23#[doc = "Field `SPI_SMEM_DIN4_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
24pub type SPI_SMEM_DIN4_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25#[doc = "Field `SPI_SMEM_DIN5_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
26pub type SPI_SMEM_DIN5_NUM_R = crate::FieldReader;
27#[doc = "Field `SPI_SMEM_DIN5_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
28pub type SPI_SMEM_DIN5_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29#[doc = "Field `SPI_SMEM_DIN6_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
30pub type SPI_SMEM_DIN6_NUM_R = crate::FieldReader;
31#[doc = "Field `SPI_SMEM_DIN6_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
32pub type SPI_SMEM_DIN6_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
33#[doc = "Field `SPI_SMEM_DIN7_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
34pub type SPI_SMEM_DIN7_NUM_R = crate::FieldReader;
35#[doc = "Field `SPI_SMEM_DIN7_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
36pub type SPI_SMEM_DIN7_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37#[doc = "Field `SPI_SMEM_DINS_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
38pub type SPI_SMEM_DINS_NUM_R = crate::FieldReader;
39#[doc = "Field `SPI_SMEM_DINS_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
40pub type SPI_SMEM_DINS_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
41impl R {
42 #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
43 #[inline(always)]
44 pub fn spi_smem_din0_num(&self) -> SPI_SMEM_DIN0_NUM_R {
45 SPI_SMEM_DIN0_NUM_R::new((self.bits & 3) as u8)
46 }
47 #[doc = "Bits 2:3 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
48 #[inline(always)]
49 pub fn spi_smem_din1_num(&self) -> SPI_SMEM_DIN1_NUM_R {
50 SPI_SMEM_DIN1_NUM_R::new(((self.bits >> 2) & 3) as u8)
51 }
52 #[doc = "Bits 4:5 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
53 #[inline(always)]
54 pub fn spi_smem_din2_num(&self) -> SPI_SMEM_DIN2_NUM_R {
55 SPI_SMEM_DIN2_NUM_R::new(((self.bits >> 4) & 3) as u8)
56 }
57 #[doc = "Bits 6:7 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
58 #[inline(always)]
59 pub fn spi_smem_din3_num(&self) -> SPI_SMEM_DIN3_NUM_R {
60 SPI_SMEM_DIN3_NUM_R::new(((self.bits >> 6) & 3) as u8)
61 }
62 #[doc = "Bits 8:9 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
63 #[inline(always)]
64 pub fn spi_smem_din4_num(&self) -> SPI_SMEM_DIN4_NUM_R {
65 SPI_SMEM_DIN4_NUM_R::new(((self.bits >> 8) & 3) as u8)
66 }
67 #[doc = "Bits 10:11 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
68 #[inline(always)]
69 pub fn spi_smem_din5_num(&self) -> SPI_SMEM_DIN5_NUM_R {
70 SPI_SMEM_DIN5_NUM_R::new(((self.bits >> 10) & 3) as u8)
71 }
72 #[doc = "Bits 12:13 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
73 #[inline(always)]
74 pub fn spi_smem_din6_num(&self) -> SPI_SMEM_DIN6_NUM_R {
75 SPI_SMEM_DIN6_NUM_R::new(((self.bits >> 12) & 3) as u8)
76 }
77 #[doc = "Bits 14:15 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
78 #[inline(always)]
79 pub fn spi_smem_din7_num(&self) -> SPI_SMEM_DIN7_NUM_R {
80 SPI_SMEM_DIN7_NUM_R::new(((self.bits >> 14) & 3) as u8)
81 }
82 #[doc = "Bits 16:17 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
83 #[inline(always)]
84 pub fn spi_smem_dins_num(&self) -> SPI_SMEM_DINS_NUM_R {
85 SPI_SMEM_DINS_NUM_R::new(((self.bits >> 16) & 3) as u8)
86 }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91 f.debug_struct("SPI_SMEM_DIN_NUM")
92 .field(
93 "spi_smem_din0_num",
94 &format_args!("{}", self.spi_smem_din0_num().bits()),
95 )
96 .field(
97 "spi_smem_din1_num",
98 &format_args!("{}", self.spi_smem_din1_num().bits()),
99 )
100 .field(
101 "spi_smem_din2_num",
102 &format_args!("{}", self.spi_smem_din2_num().bits()),
103 )
104 .field(
105 "spi_smem_din3_num",
106 &format_args!("{}", self.spi_smem_din3_num().bits()),
107 )
108 .field(
109 "spi_smem_din4_num",
110 &format_args!("{}", self.spi_smem_din4_num().bits()),
111 )
112 .field(
113 "spi_smem_din5_num",
114 &format_args!("{}", self.spi_smem_din5_num().bits()),
115 )
116 .field(
117 "spi_smem_din6_num",
118 &format_args!("{}", self.spi_smem_din6_num().bits()),
119 )
120 .field(
121 "spi_smem_din7_num",
122 &format_args!("{}", self.spi_smem_din7_num().bits()),
123 )
124 .field(
125 "spi_smem_dins_num",
126 &format_args!("{}", self.spi_smem_dins_num().bits()),
127 )
128 .finish()
129 }
130}
131#[cfg(feature = "impl-register-debug")]
132impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DIN_NUM_SPEC> {
133 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
134 core::fmt::Debug::fmt(&self.read(), f)
135 }
136}
137impl W {
138 #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
139 #[inline(always)]
140 #[must_use]
141 pub fn spi_smem_din0_num(&mut self) -> SPI_SMEM_DIN0_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
142 SPI_SMEM_DIN0_NUM_W::new(self, 0)
143 }
144 #[doc = "Bits 2:3 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
145 #[inline(always)]
146 #[must_use]
147 pub fn spi_smem_din1_num(&mut self) -> SPI_SMEM_DIN1_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
148 SPI_SMEM_DIN1_NUM_W::new(self, 2)
149 }
150 #[doc = "Bits 4:5 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
151 #[inline(always)]
152 #[must_use]
153 pub fn spi_smem_din2_num(&mut self) -> SPI_SMEM_DIN2_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
154 SPI_SMEM_DIN2_NUM_W::new(self, 4)
155 }
156 #[doc = "Bits 6:7 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
157 #[inline(always)]
158 #[must_use]
159 pub fn spi_smem_din3_num(&mut self) -> SPI_SMEM_DIN3_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
160 SPI_SMEM_DIN3_NUM_W::new(self, 6)
161 }
162 #[doc = "Bits 8:9 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
163 #[inline(always)]
164 #[must_use]
165 pub fn spi_smem_din4_num(&mut self) -> SPI_SMEM_DIN4_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
166 SPI_SMEM_DIN4_NUM_W::new(self, 8)
167 }
168 #[doc = "Bits 10:11 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
169 #[inline(always)]
170 #[must_use]
171 pub fn spi_smem_din5_num(&mut self) -> SPI_SMEM_DIN5_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
172 SPI_SMEM_DIN5_NUM_W::new(self, 10)
173 }
174 #[doc = "Bits 12:13 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
175 #[inline(always)]
176 #[must_use]
177 pub fn spi_smem_din6_num(&mut self) -> SPI_SMEM_DIN6_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
178 SPI_SMEM_DIN6_NUM_W::new(self, 12)
179 }
180 #[doc = "Bits 14:15 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
181 #[inline(always)]
182 #[must_use]
183 pub fn spi_smem_din7_num(&mut self) -> SPI_SMEM_DIN7_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
184 SPI_SMEM_DIN7_NUM_W::new(self, 14)
185 }
186 #[doc = "Bits 16:17 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
187 #[inline(always)]
188 #[must_use]
189 pub fn spi_smem_dins_num(&mut self) -> SPI_SMEM_DINS_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
190 SPI_SMEM_DINS_NUM_W::new(self, 16)
191 }
192}
193#[doc = "MSPI external RAM input timing delay number control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_din_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_din_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
194pub struct SPI_SMEM_DIN_NUM_SPEC;
195impl crate::RegisterSpec for SPI_SMEM_DIN_NUM_SPEC {
196 type Ux = u32;
197}
198#[doc = "`read()` method returns [`spi_smem_din_num::R`](R) reader structure"]
199impl crate::Readable for SPI_SMEM_DIN_NUM_SPEC {}
200#[doc = "`write(|w| ..)` method takes [`spi_smem_din_num::W`](W) writer structure"]
201impl crate::Writable for SPI_SMEM_DIN_NUM_SPEC {
202 type Safety = crate::Unsafe;
203 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
204 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
205}
206#[doc = "`reset()` method sets SPI_SMEM_DIN_NUM to value 0"]
207impl crate::Resettable for SPI_SMEM_DIN_NUM_SPEC {
208 const RESET_VALUE: u32 = 0;
209}