esp32p4/spi0/
ecc_err_addr.rs

1#[doc = "Register `ECC_ERR_ADDR` reader"]
2pub type R = crate::R<ECC_ERR_ADDR_SPEC>;
3#[doc = "Field `ECC_ERR_ADDR` reader - This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set."]
4pub type ECC_ERR_ADDR_R = crate::FieldReader<u32>;
5impl R {
6    #[doc = "Bits 0:26 - This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set."]
7    #[inline(always)]
8    pub fn ecc_err_addr(&self) -> ECC_ERR_ADDR_R {
9        ECC_ERR_ADDR_R::new(self.bits & 0x07ff_ffff)
10    }
11}
12#[cfg(feature = "impl-register-debug")]
13impl core::fmt::Debug for R {
14    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
15        f.debug_struct("ECC_ERR_ADDR")
16            .field(
17                "ecc_err_addr",
18                &format_args!("{}", self.ecc_err_addr().bits()),
19            )
20            .finish()
21    }
22}
23#[cfg(feature = "impl-register-debug")]
24impl core::fmt::Debug for crate::generic::Reg<ECC_ERR_ADDR_SPEC> {
25    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
26        core::fmt::Debug::fmt(&self.read(), f)
27    }
28}
29#[doc = "MSPI ECC error address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecc_err_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30pub struct ECC_ERR_ADDR_SPEC;
31impl crate::RegisterSpec for ECC_ERR_ADDR_SPEC {
32    type Ux = u32;
33}
34#[doc = "`read()` method returns [`ecc_err_addr::R`](R) reader structure"]
35impl crate::Readable for ECC_ERR_ADDR_SPEC {}
36#[doc = "`reset()` method sets ECC_ERR_ADDR to value 0"]
37impl crate::Resettable for ECC_ERR_ADDR_SPEC {
38    const RESET_VALUE: u32 = 0;
39}
esp32p4/spi0/ecc_err_addr.rs

esp32p4/spi0/
ecc_err_addr.rs
