1#[doc = "Register `TASK_ST5_CLR` writer"]
2pub type W = crate::W<TASK_ST5_CLR_SPEC>;
3#[doc = "Field `REGDMA_TASK_START0_ST_CLR` writer - Configures whether or not to clear REGDMA_task_start0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
4pub type REGDMA_TASK_START0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `REGDMA_TASK_START1_ST_CLR` writer - Configures whether or not to clear REGDMA_task_start1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
6pub type REGDMA_TASK_START1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `REGDMA_TASK_START2_ST_CLR` writer - Configures whether or not to clear REGDMA_task_start2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
8pub type REGDMA_TASK_START2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `REGDMA_TASK_START3_ST_CLR` writer - Configures whether or not to clear REGDMA_task_start3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
10pub type REGDMA_TASK_START3_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `TMPSNSR_TASK_START_SAMPLE_ST_CLR` writer - Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
12pub type TMPSNSR_TASK_START_SAMPLE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TMPSNSR_TASK_STOP_SAMPLE_ST_CLR` writer - Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
14pub type TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `I2S0_TASK_START_RX_ST_CLR` writer - Configures whether or not to clear I2S0_task_start_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
16pub type I2S0_TASK_START_RX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `I2S0_TASK_START_TX_ST_CLR` writer - Configures whether or not to clear I2S0_task_start_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
18pub type I2S0_TASK_START_TX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `I2S0_TASK_STOP_RX_ST_CLR` writer - Configures whether or not to clear I2S0_task_stop_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
20pub type I2S0_TASK_STOP_RX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `I2S0_TASK_STOP_TX_ST_CLR` writer - Configures whether or not to clear I2S0_task_stop_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
22pub type I2S0_TASK_STOP_TX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `I2S1_TASK_START_RX_ST_CLR` writer - Configures whether or not to clear I2S1_task_start_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
24pub type I2S1_TASK_START_RX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `I2S1_TASK_START_TX_ST_CLR` writer - Configures whether or not to clear I2S1_task_start_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
26pub type I2S1_TASK_START_TX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `I2S1_TASK_STOP_RX_ST_CLR` writer - Configures whether or not to clear I2S1_task_stop_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
28pub type I2S1_TASK_STOP_RX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `I2S1_TASK_STOP_TX_ST_CLR` writer - Configures whether or not to clear I2S1_task_stop_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
30pub type I2S1_TASK_STOP_TX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `I2S2_TASK_START_RX_ST_CLR` writer - Configures whether or not to clear I2S2_task_start_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
32pub type I2S2_TASK_START_RX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `I2S2_TASK_START_TX_ST_CLR` writer - Configures whether or not to clear I2S2_task_start_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
34pub type I2S2_TASK_START_TX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `I2S2_TASK_STOP_RX_ST_CLR` writer - Configures whether or not to clear I2S2_task_stop_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
36pub type I2S2_TASK_STOP_RX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `I2S2_TASK_STOP_TX_ST_CLR` writer - Configures whether or not to clear I2S2_task_stop_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
38pub type I2S2_TASK_STOP_TX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `ULP_TASK_WAKEUP_CPU_ST_CLR` writer - Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
40pub type ULP_TASK_WAKEUP_CPU_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `ULP_TASK_INT_CPU_ST_CLR` writer - Configures whether or not to clear ULP_task_int_cpu trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
42pub type ULP_TASK_INT_CPU_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
43#[doc = "Field `RTC_TASK_START_ST_CLR` writer - Configures whether or not to clear RTC_task_start trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
44pub type RTC_TASK_START_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `RTC_TASK_STOP_ST_CLR` writer - Configures whether or not to clear RTC_task_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
46pub type RTC_TASK_STOP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `RTC_TASK_CLR_ST_CLR` writer - Configures whether or not to clear RTC_task_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
48pub type RTC_TASK_CLR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `RTC_TASK_TRIGGERFLW_ST_CLR` writer - Configures whether or not to clear RTC_task_triggerflw trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
50pub type RTC_TASK_TRIGGERFLW_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
51#[doc = "Field `PDMA_AHB_TASK_IN_START_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_task_in_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
52pub type PDMA_AHB_TASK_IN_START_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `PDMA_AHB_TASK_IN_START_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_task_in_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
54pub type PDMA_AHB_TASK_IN_START_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
55#[doc = "Field `PDMA_AHB_TASK_IN_START_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_task_in_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
56pub type PDMA_AHB_TASK_IN_START_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `PDMA_AHB_TASK_OUT_START_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_task_out_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
58pub type PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
59#[doc = "Field `PDMA_AHB_TASK_OUT_START_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_task_out_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
60pub type PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `PDMA_AHB_TASK_OUT_START_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_task_out_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
62pub type PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
63#[doc = "Field `PDMA_AXI_TASK_IN_START_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_task_in_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
64pub type PDMA_AXI_TASK_IN_START_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `PDMA_AXI_TASK_IN_START_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_task_in_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
66pub type PDMA_AXI_TASK_IN_START_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
67#[cfg(feature = "impl-register-debug")]
68impl core::fmt::Debug for crate::generic::Reg<TASK_ST5_CLR_SPEC> {
69 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
70 write!(f, "(not readable)")
71 }
72}
73impl W {
74 #[doc = "Bit 0 - Configures whether or not to clear REGDMA_task_start0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
75 #[inline(always)]
76 #[must_use]
77 pub fn regdma_task_start0_st_clr(&mut self) -> REGDMA_TASK_START0_ST_CLR_W<TASK_ST5_CLR_SPEC> {
78 REGDMA_TASK_START0_ST_CLR_W::new(self, 0)
79 }
80 #[doc = "Bit 1 - Configures whether or not to clear REGDMA_task_start1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
81 #[inline(always)]
82 #[must_use]
83 pub fn regdma_task_start1_st_clr(&mut self) -> REGDMA_TASK_START1_ST_CLR_W<TASK_ST5_CLR_SPEC> {
84 REGDMA_TASK_START1_ST_CLR_W::new(self, 1)
85 }
86 #[doc = "Bit 2 - Configures whether or not to clear REGDMA_task_start2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
87 #[inline(always)]
88 #[must_use]
89 pub fn regdma_task_start2_st_clr(&mut self) -> REGDMA_TASK_START2_ST_CLR_W<TASK_ST5_CLR_SPEC> {
90 REGDMA_TASK_START2_ST_CLR_W::new(self, 2)
91 }
92 #[doc = "Bit 3 - Configures whether or not to clear REGDMA_task_start3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
93 #[inline(always)]
94 #[must_use]
95 pub fn regdma_task_start3_st_clr(&mut self) -> REGDMA_TASK_START3_ST_CLR_W<TASK_ST5_CLR_SPEC> {
96 REGDMA_TASK_START3_ST_CLR_W::new(self, 3)
97 }
98 #[doc = "Bit 4 - Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
99 #[inline(always)]
100 #[must_use]
101 pub fn tmpsnsr_task_start_sample_st_clr(
102 &mut self,
103 ) -> TMPSNSR_TASK_START_SAMPLE_ST_CLR_W<TASK_ST5_CLR_SPEC> {
104 TMPSNSR_TASK_START_SAMPLE_ST_CLR_W::new(self, 4)
105 }
106 #[doc = "Bit 5 - Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
107 #[inline(always)]
108 #[must_use]
109 pub fn tmpsnsr_task_stop_sample_st_clr(
110 &mut self,
111 ) -> TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_W<TASK_ST5_CLR_SPEC> {
112 TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_W::new(self, 5)
113 }
114 #[doc = "Bit 6 - Configures whether or not to clear I2S0_task_start_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
115 #[inline(always)]
116 #[must_use]
117 pub fn i2s0_task_start_rx_st_clr(&mut self) -> I2S0_TASK_START_RX_ST_CLR_W<TASK_ST5_CLR_SPEC> {
118 I2S0_TASK_START_RX_ST_CLR_W::new(self, 6)
119 }
120 #[doc = "Bit 7 - Configures whether or not to clear I2S0_task_start_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
121 #[inline(always)]
122 #[must_use]
123 pub fn i2s0_task_start_tx_st_clr(&mut self) -> I2S0_TASK_START_TX_ST_CLR_W<TASK_ST5_CLR_SPEC> {
124 I2S0_TASK_START_TX_ST_CLR_W::new(self, 7)
125 }
126 #[doc = "Bit 8 - Configures whether or not to clear I2S0_task_stop_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
127 #[inline(always)]
128 #[must_use]
129 pub fn i2s0_task_stop_rx_st_clr(&mut self) -> I2S0_TASK_STOP_RX_ST_CLR_W<TASK_ST5_CLR_SPEC> {
130 I2S0_TASK_STOP_RX_ST_CLR_W::new(self, 8)
131 }
132 #[doc = "Bit 9 - Configures whether or not to clear I2S0_task_stop_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
133 #[inline(always)]
134 #[must_use]
135 pub fn i2s0_task_stop_tx_st_clr(&mut self) -> I2S0_TASK_STOP_TX_ST_CLR_W<TASK_ST5_CLR_SPEC> {
136 I2S0_TASK_STOP_TX_ST_CLR_W::new(self, 9)
137 }
138 #[doc = "Bit 10 - Configures whether or not to clear I2S1_task_start_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
139 #[inline(always)]
140 #[must_use]
141 pub fn i2s1_task_start_rx_st_clr(&mut self) -> I2S1_TASK_START_RX_ST_CLR_W<TASK_ST5_CLR_SPEC> {
142 I2S1_TASK_START_RX_ST_CLR_W::new(self, 10)
143 }
144 #[doc = "Bit 11 - Configures whether or not to clear I2S1_task_start_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
145 #[inline(always)]
146 #[must_use]
147 pub fn i2s1_task_start_tx_st_clr(&mut self) -> I2S1_TASK_START_TX_ST_CLR_W<TASK_ST5_CLR_SPEC> {
148 I2S1_TASK_START_TX_ST_CLR_W::new(self, 11)
149 }
150 #[doc = "Bit 12 - Configures whether or not to clear I2S1_task_stop_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
151 #[inline(always)]
152 #[must_use]
153 pub fn i2s1_task_stop_rx_st_clr(&mut self) -> I2S1_TASK_STOP_RX_ST_CLR_W<TASK_ST5_CLR_SPEC> {
154 I2S1_TASK_STOP_RX_ST_CLR_W::new(self, 12)
155 }
156 #[doc = "Bit 13 - Configures whether or not to clear I2S1_task_stop_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
157 #[inline(always)]
158 #[must_use]
159 pub fn i2s1_task_stop_tx_st_clr(&mut self) -> I2S1_TASK_STOP_TX_ST_CLR_W<TASK_ST5_CLR_SPEC> {
160 I2S1_TASK_STOP_TX_ST_CLR_W::new(self, 13)
161 }
162 #[doc = "Bit 14 - Configures whether or not to clear I2S2_task_start_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
163 #[inline(always)]
164 #[must_use]
165 pub fn i2s2_task_start_rx_st_clr(&mut self) -> I2S2_TASK_START_RX_ST_CLR_W<TASK_ST5_CLR_SPEC> {
166 I2S2_TASK_START_RX_ST_CLR_W::new(self, 14)
167 }
168 #[doc = "Bit 15 - Configures whether or not to clear I2S2_task_start_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
169 #[inline(always)]
170 #[must_use]
171 pub fn i2s2_task_start_tx_st_clr(&mut self) -> I2S2_TASK_START_TX_ST_CLR_W<TASK_ST5_CLR_SPEC> {
172 I2S2_TASK_START_TX_ST_CLR_W::new(self, 15)
173 }
174 #[doc = "Bit 16 - Configures whether or not to clear I2S2_task_stop_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
175 #[inline(always)]
176 #[must_use]
177 pub fn i2s2_task_stop_rx_st_clr(&mut self) -> I2S2_TASK_STOP_RX_ST_CLR_W<TASK_ST5_CLR_SPEC> {
178 I2S2_TASK_STOP_RX_ST_CLR_W::new(self, 16)
179 }
180 #[doc = "Bit 17 - Configures whether or not to clear I2S2_task_stop_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
181 #[inline(always)]
182 #[must_use]
183 pub fn i2s2_task_stop_tx_st_clr(&mut self) -> I2S2_TASK_STOP_TX_ST_CLR_W<TASK_ST5_CLR_SPEC> {
184 I2S2_TASK_STOP_TX_ST_CLR_W::new(self, 17)
185 }
186 #[doc = "Bit 18 - Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
187 #[inline(always)]
188 #[must_use]
189 pub fn ulp_task_wakeup_cpu_st_clr(
190 &mut self,
191 ) -> ULP_TASK_WAKEUP_CPU_ST_CLR_W<TASK_ST5_CLR_SPEC> {
192 ULP_TASK_WAKEUP_CPU_ST_CLR_W::new(self, 18)
193 }
194 #[doc = "Bit 19 - Configures whether or not to clear ULP_task_int_cpu trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
195 #[inline(always)]
196 #[must_use]
197 pub fn ulp_task_int_cpu_st_clr(&mut self) -> ULP_TASK_INT_CPU_ST_CLR_W<TASK_ST5_CLR_SPEC> {
198 ULP_TASK_INT_CPU_ST_CLR_W::new(self, 19)
199 }
200 #[doc = "Bit 20 - Configures whether or not to clear RTC_task_start trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
201 #[inline(always)]
202 #[must_use]
203 pub fn rtc_task_start_st_clr(&mut self) -> RTC_TASK_START_ST_CLR_W<TASK_ST5_CLR_SPEC> {
204 RTC_TASK_START_ST_CLR_W::new(self, 20)
205 }
206 #[doc = "Bit 21 - Configures whether or not to clear RTC_task_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
207 #[inline(always)]
208 #[must_use]
209 pub fn rtc_task_stop_st_clr(&mut self) -> RTC_TASK_STOP_ST_CLR_W<TASK_ST5_CLR_SPEC> {
210 RTC_TASK_STOP_ST_CLR_W::new(self, 21)
211 }
212 #[doc = "Bit 22 - Configures whether or not to clear RTC_task_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
213 #[inline(always)]
214 #[must_use]
215 pub fn rtc_task_clr_st_clr(&mut self) -> RTC_TASK_CLR_ST_CLR_W<TASK_ST5_CLR_SPEC> {
216 RTC_TASK_CLR_ST_CLR_W::new(self, 22)
217 }
218 #[doc = "Bit 23 - Configures whether or not to clear RTC_task_triggerflw trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
219 #[inline(always)]
220 #[must_use]
221 pub fn rtc_task_triggerflw_st_clr(
222 &mut self,
223 ) -> RTC_TASK_TRIGGERFLW_ST_CLR_W<TASK_ST5_CLR_SPEC> {
224 RTC_TASK_TRIGGERFLW_ST_CLR_W::new(self, 23)
225 }
226 #[doc = "Bit 24 - Configures whether or not to clear PDMA_AHB_task_in_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
227 #[inline(always)]
228 #[must_use]
229 pub fn pdma_ahb_task_in_start_ch0_st_clr(
230 &mut self,
231 ) -> PDMA_AHB_TASK_IN_START_CH0_ST_CLR_W<TASK_ST5_CLR_SPEC> {
232 PDMA_AHB_TASK_IN_START_CH0_ST_CLR_W::new(self, 24)
233 }
234 #[doc = "Bit 25 - Configures whether or not to clear PDMA_AHB_task_in_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
235 #[inline(always)]
236 #[must_use]
237 pub fn pdma_ahb_task_in_start_ch1_st_clr(
238 &mut self,
239 ) -> PDMA_AHB_TASK_IN_START_CH1_ST_CLR_W<TASK_ST5_CLR_SPEC> {
240 PDMA_AHB_TASK_IN_START_CH1_ST_CLR_W::new(self, 25)
241 }
242 #[doc = "Bit 26 - Configures whether or not to clear PDMA_AHB_task_in_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
243 #[inline(always)]
244 #[must_use]
245 pub fn pdma_ahb_task_in_start_ch2_st_clr(
246 &mut self,
247 ) -> PDMA_AHB_TASK_IN_START_CH2_ST_CLR_W<TASK_ST5_CLR_SPEC> {
248 PDMA_AHB_TASK_IN_START_CH2_ST_CLR_W::new(self, 26)
249 }
250 #[doc = "Bit 27 - Configures whether or not to clear PDMA_AHB_task_out_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
251 #[inline(always)]
252 #[must_use]
253 pub fn pdma_ahb_task_out_start_ch0_st_clr(
254 &mut self,
255 ) -> PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_W<TASK_ST5_CLR_SPEC> {
256 PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_W::new(self, 27)
257 }
258 #[doc = "Bit 28 - Configures whether or not to clear PDMA_AHB_task_out_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
259 #[inline(always)]
260 #[must_use]
261 pub fn pdma_ahb_task_out_start_ch1_st_clr(
262 &mut self,
263 ) -> PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_W<TASK_ST5_CLR_SPEC> {
264 PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_W::new(self, 28)
265 }
266 #[doc = "Bit 29 - Configures whether or not to clear PDMA_AHB_task_out_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
267 #[inline(always)]
268 #[must_use]
269 pub fn pdma_ahb_task_out_start_ch2_st_clr(
270 &mut self,
271 ) -> PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_W<TASK_ST5_CLR_SPEC> {
272 PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_W::new(self, 29)
273 }
274 #[doc = "Bit 30 - Configures whether or not to clear PDMA_AXI_task_in_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
275 #[inline(always)]
276 #[must_use]
277 pub fn pdma_axi_task_in_start_ch0_st_clr(
278 &mut self,
279 ) -> PDMA_AXI_TASK_IN_START_CH0_ST_CLR_W<TASK_ST5_CLR_SPEC> {
280 PDMA_AXI_TASK_IN_START_CH0_ST_CLR_W::new(self, 30)
281 }
282 #[doc = "Bit 31 - Configures whether or not to clear PDMA_AXI_task_in_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
283 #[inline(always)]
284 #[must_use]
285 pub fn pdma_axi_task_in_start_ch1_st_clr(
286 &mut self,
287 ) -> PDMA_AXI_TASK_IN_START_CH1_ST_CLR_W<TASK_ST5_CLR_SPEC> {
288 PDMA_AXI_TASK_IN_START_CH1_ST_CLR_W::new(self, 31)
289 }
290}
291#[doc = "Tasks trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st5_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
292pub struct TASK_ST5_CLR_SPEC;
293impl crate::RegisterSpec for TASK_ST5_CLR_SPEC {
294 type Ux = u32;
295}
296#[doc = "`write(|w| ..)` method takes [`task_st5_clr::W`](W) writer structure"]
297impl crate::Writable for TASK_ST5_CLR_SPEC {
298 type Safety = crate::Unsafe;
299 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
300 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
301}
302#[doc = "`reset()` method sets TASK_ST5_CLR to value 0"]
303impl crate::Resettable for TASK_ST5_CLR_SPEC {
304 const RESET_VALUE: u32 = 0;
305}