esp32p4/soc_etm/
evt_st0_clr.rs

1#[doc = "Register `EVT_ST0_CLR` writer"]
2pub type W = crate::W<EVT_ST0_CLR_SPEC>;
3#[doc = "Field `GPIO_EVT_CH0_RISE_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
4pub type GPIO_EVT_CH0_RISE_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `GPIO_EVT_CH1_RISE_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
6pub type GPIO_EVT_CH1_RISE_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `GPIO_EVT_CH2_RISE_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
8pub type GPIO_EVT_CH2_RISE_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `GPIO_EVT_CH3_RISE_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
10pub type GPIO_EVT_CH3_RISE_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `GPIO_EVT_CH4_RISE_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
12pub type GPIO_EVT_CH4_RISE_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `GPIO_EVT_CH5_RISE_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
14pub type GPIO_EVT_CH5_RISE_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `GPIO_EVT_CH6_RISE_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
16pub type GPIO_EVT_CH6_RISE_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `GPIO_EVT_CH7_RISE_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
18pub type GPIO_EVT_CH7_RISE_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `GPIO_EVT_CH0_FALL_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
20pub type GPIO_EVT_CH0_FALL_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `GPIO_EVT_CH1_FALL_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
22pub type GPIO_EVT_CH1_FALL_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `GPIO_EVT_CH2_FALL_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
24pub type GPIO_EVT_CH2_FALL_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `GPIO_EVT_CH3_FALL_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
26pub type GPIO_EVT_CH3_FALL_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `GPIO_EVT_CH4_FALL_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
28pub type GPIO_EVT_CH4_FALL_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `GPIO_EVT_CH5_FALL_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
30pub type GPIO_EVT_CH5_FALL_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `GPIO_EVT_CH6_FALL_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
32pub type GPIO_EVT_CH6_FALL_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `GPIO_EVT_CH7_FALL_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
34pub type GPIO_EVT_CH7_FALL_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `GPIO_EVT_CH0_ANY_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
36pub type GPIO_EVT_CH0_ANY_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `GPIO_EVT_CH1_ANY_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
38pub type GPIO_EVT_CH1_ANY_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `GPIO_EVT_CH2_ANY_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
40pub type GPIO_EVT_CH2_ANY_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `GPIO_EVT_CH3_ANY_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
42pub type GPIO_EVT_CH3_ANY_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
43#[doc = "Field `GPIO_EVT_CH4_ANY_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
44pub type GPIO_EVT_CH4_ANY_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `GPIO_EVT_CH5_ANY_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
46pub type GPIO_EVT_CH5_ANY_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `GPIO_EVT_CH6_ANY_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
48pub type GPIO_EVT_CH6_ANY_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `GPIO_EVT_CH7_ANY_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
50pub type GPIO_EVT_CH7_ANY_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
51#[doc = "Field `GPIO_EVT_ZERO_DET_POS0_ST_CLR` writer - Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
52pub type GPIO_EVT_ZERO_DET_POS0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `GPIO_EVT_ZERO_DET_NEG0_ST_CLR` writer - Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
54pub type GPIO_EVT_ZERO_DET_NEG0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
55#[doc = "Field `GPIO_EVT_ZERO_DET_POS1_ST_CLR` writer - Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
56pub type GPIO_EVT_ZERO_DET_POS1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `GPIO_EVT_ZERO_DET_NEG1_ST_CLR` writer - Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
58pub type GPIO_EVT_ZERO_DET_NEG1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
59#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR` writer - Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
60pub type LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR` writer - Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
62pub type LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
63#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR` writer - Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
64pub type LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR` writer - Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
66pub type LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
67#[cfg(feature = "impl-register-debug")]
68impl core::fmt::Debug for crate::generic::Reg<EVT_ST0_CLR_SPEC> {
69    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
70        write!(f, "(not readable)")
71    }
72}
73impl W {
74    #[doc = "Bit 0 - Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
75    #[inline(always)]
76    #[must_use]
77    pub fn gpio_evt_ch0_rise_edge_st_clr(
78        &mut self,
79    ) -> GPIO_EVT_CH0_RISE_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
80        GPIO_EVT_CH0_RISE_EDGE_ST_CLR_W::new(self, 0)
81    }
82    #[doc = "Bit 1 - Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
83    #[inline(always)]
84    #[must_use]
85    pub fn gpio_evt_ch1_rise_edge_st_clr(
86        &mut self,
87    ) -> GPIO_EVT_CH1_RISE_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
88        GPIO_EVT_CH1_RISE_EDGE_ST_CLR_W::new(self, 1)
89    }
90    #[doc = "Bit 2 - Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
91    #[inline(always)]
92    #[must_use]
93    pub fn gpio_evt_ch2_rise_edge_st_clr(
94        &mut self,
95    ) -> GPIO_EVT_CH2_RISE_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
96        GPIO_EVT_CH2_RISE_EDGE_ST_CLR_W::new(self, 2)
97    }
98    #[doc = "Bit 3 - Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
99    #[inline(always)]
100    #[must_use]
101    pub fn gpio_evt_ch3_rise_edge_st_clr(
102        &mut self,
103    ) -> GPIO_EVT_CH3_RISE_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
104        GPIO_EVT_CH3_RISE_EDGE_ST_CLR_W::new(self, 3)
105    }
106    #[doc = "Bit 4 - Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
107    #[inline(always)]
108    #[must_use]
109    pub fn gpio_evt_ch4_rise_edge_st_clr(
110        &mut self,
111    ) -> GPIO_EVT_CH4_RISE_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
112        GPIO_EVT_CH4_RISE_EDGE_ST_CLR_W::new(self, 4)
113    }
114    #[doc = "Bit 5 - Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
115    #[inline(always)]
116    #[must_use]
117    pub fn gpio_evt_ch5_rise_edge_st_clr(
118        &mut self,
119    ) -> GPIO_EVT_CH5_RISE_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
120        GPIO_EVT_CH5_RISE_EDGE_ST_CLR_W::new(self, 5)
121    }
122    #[doc = "Bit 6 - Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
123    #[inline(always)]
124    #[must_use]
125    pub fn gpio_evt_ch6_rise_edge_st_clr(
126        &mut self,
127    ) -> GPIO_EVT_CH6_RISE_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
128        GPIO_EVT_CH6_RISE_EDGE_ST_CLR_W::new(self, 6)
129    }
130    #[doc = "Bit 7 - Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
131    #[inline(always)]
132    #[must_use]
133    pub fn gpio_evt_ch7_rise_edge_st_clr(
134        &mut self,
135    ) -> GPIO_EVT_CH7_RISE_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
136        GPIO_EVT_CH7_RISE_EDGE_ST_CLR_W::new(self, 7)
137    }
138    #[doc = "Bit 8 - Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
139    #[inline(always)]
140    #[must_use]
141    pub fn gpio_evt_ch0_fall_edge_st_clr(
142        &mut self,
143    ) -> GPIO_EVT_CH0_FALL_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
144        GPIO_EVT_CH0_FALL_EDGE_ST_CLR_W::new(self, 8)
145    }
146    #[doc = "Bit 9 - Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
147    #[inline(always)]
148    #[must_use]
149    pub fn gpio_evt_ch1_fall_edge_st_clr(
150        &mut self,
151    ) -> GPIO_EVT_CH1_FALL_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
152        GPIO_EVT_CH1_FALL_EDGE_ST_CLR_W::new(self, 9)
153    }
154    #[doc = "Bit 10 - Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
155    #[inline(always)]
156    #[must_use]
157    pub fn gpio_evt_ch2_fall_edge_st_clr(
158        &mut self,
159    ) -> GPIO_EVT_CH2_FALL_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
160        GPIO_EVT_CH2_FALL_EDGE_ST_CLR_W::new(self, 10)
161    }
162    #[doc = "Bit 11 - Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
163    #[inline(always)]
164    #[must_use]
165    pub fn gpio_evt_ch3_fall_edge_st_clr(
166        &mut self,
167    ) -> GPIO_EVT_CH3_FALL_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
168        GPIO_EVT_CH3_FALL_EDGE_ST_CLR_W::new(self, 11)
169    }
170    #[doc = "Bit 12 - Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
171    #[inline(always)]
172    #[must_use]
173    pub fn gpio_evt_ch4_fall_edge_st_clr(
174        &mut self,
175    ) -> GPIO_EVT_CH4_FALL_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
176        GPIO_EVT_CH4_FALL_EDGE_ST_CLR_W::new(self, 12)
177    }
178    #[doc = "Bit 13 - Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
179    #[inline(always)]
180    #[must_use]
181    pub fn gpio_evt_ch5_fall_edge_st_clr(
182        &mut self,
183    ) -> GPIO_EVT_CH5_FALL_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
184        GPIO_EVT_CH5_FALL_EDGE_ST_CLR_W::new(self, 13)
185    }
186    #[doc = "Bit 14 - Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
187    #[inline(always)]
188    #[must_use]
189    pub fn gpio_evt_ch6_fall_edge_st_clr(
190        &mut self,
191    ) -> GPIO_EVT_CH6_FALL_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
192        GPIO_EVT_CH6_FALL_EDGE_ST_CLR_W::new(self, 14)
193    }
194    #[doc = "Bit 15 - Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
195    #[inline(always)]
196    #[must_use]
197    pub fn gpio_evt_ch7_fall_edge_st_clr(
198        &mut self,
199    ) -> GPIO_EVT_CH7_FALL_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
200        GPIO_EVT_CH7_FALL_EDGE_ST_CLR_W::new(self, 15)
201    }
202    #[doc = "Bit 16 - Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
203    #[inline(always)]
204    #[must_use]
205    pub fn gpio_evt_ch0_any_edge_st_clr(
206        &mut self,
207    ) -> GPIO_EVT_CH0_ANY_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
208        GPIO_EVT_CH0_ANY_EDGE_ST_CLR_W::new(self, 16)
209    }
210    #[doc = "Bit 17 - Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
211    #[inline(always)]
212    #[must_use]
213    pub fn gpio_evt_ch1_any_edge_st_clr(
214        &mut self,
215    ) -> GPIO_EVT_CH1_ANY_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
216        GPIO_EVT_CH1_ANY_EDGE_ST_CLR_W::new(self, 17)
217    }
218    #[doc = "Bit 18 - Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
219    #[inline(always)]
220    #[must_use]
221    pub fn gpio_evt_ch2_any_edge_st_clr(
222        &mut self,
223    ) -> GPIO_EVT_CH2_ANY_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
224        GPIO_EVT_CH2_ANY_EDGE_ST_CLR_W::new(self, 18)
225    }
226    #[doc = "Bit 19 - Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
227    #[inline(always)]
228    #[must_use]
229    pub fn gpio_evt_ch3_any_edge_st_clr(
230        &mut self,
231    ) -> GPIO_EVT_CH3_ANY_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
232        GPIO_EVT_CH3_ANY_EDGE_ST_CLR_W::new(self, 19)
233    }
234    #[doc = "Bit 20 - Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
235    #[inline(always)]
236    #[must_use]
237    pub fn gpio_evt_ch4_any_edge_st_clr(
238        &mut self,
239    ) -> GPIO_EVT_CH4_ANY_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
240        GPIO_EVT_CH4_ANY_EDGE_ST_CLR_W::new(self, 20)
241    }
242    #[doc = "Bit 21 - Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
243    #[inline(always)]
244    #[must_use]
245    pub fn gpio_evt_ch5_any_edge_st_clr(
246        &mut self,
247    ) -> GPIO_EVT_CH5_ANY_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
248        GPIO_EVT_CH5_ANY_EDGE_ST_CLR_W::new(self, 21)
249    }
250    #[doc = "Bit 22 - Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
251    #[inline(always)]
252    #[must_use]
253    pub fn gpio_evt_ch6_any_edge_st_clr(
254        &mut self,
255    ) -> GPIO_EVT_CH6_ANY_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
256        GPIO_EVT_CH6_ANY_EDGE_ST_CLR_W::new(self, 22)
257    }
258    #[doc = "Bit 23 - Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
259    #[inline(always)]
260    #[must_use]
261    pub fn gpio_evt_ch7_any_edge_st_clr(
262        &mut self,
263    ) -> GPIO_EVT_CH7_ANY_EDGE_ST_CLR_W<EVT_ST0_CLR_SPEC> {
264        GPIO_EVT_CH7_ANY_EDGE_ST_CLR_W::new(self, 23)
265    }
266    #[doc = "Bit 24 - Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
267    #[inline(always)]
268    #[must_use]
269    pub fn gpio_evt_zero_det_pos0_st_clr(
270        &mut self,
271    ) -> GPIO_EVT_ZERO_DET_POS0_ST_CLR_W<EVT_ST0_CLR_SPEC> {
272        GPIO_EVT_ZERO_DET_POS0_ST_CLR_W::new(self, 24)
273    }
274    #[doc = "Bit 25 - Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
275    #[inline(always)]
276    #[must_use]
277    pub fn gpio_evt_zero_det_neg0_st_clr(
278        &mut self,
279    ) -> GPIO_EVT_ZERO_DET_NEG0_ST_CLR_W<EVT_ST0_CLR_SPEC> {
280        GPIO_EVT_ZERO_DET_NEG0_ST_CLR_W::new(self, 25)
281    }
282    #[doc = "Bit 26 - Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
283    #[inline(always)]
284    #[must_use]
285    pub fn gpio_evt_zero_det_pos1_st_clr(
286        &mut self,
287    ) -> GPIO_EVT_ZERO_DET_POS1_ST_CLR_W<EVT_ST0_CLR_SPEC> {
288        GPIO_EVT_ZERO_DET_POS1_ST_CLR_W::new(self, 26)
289    }
290    #[doc = "Bit 27 - Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
291    #[inline(always)]
292    #[must_use]
293    pub fn gpio_evt_zero_det_neg1_st_clr(
294        &mut self,
295    ) -> GPIO_EVT_ZERO_DET_NEG1_ST_CLR_W<EVT_ST0_CLR_SPEC> {
296        GPIO_EVT_ZERO_DET_NEG1_ST_CLR_W::new(self, 27)
297    }
298    #[doc = "Bit 28 - Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
299    #[inline(always)]
300    #[must_use]
301    pub fn ledc_evt_duty_chng_end_ch0_st_clr(
302        &mut self,
303    ) -> LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_W<EVT_ST0_CLR_SPEC> {
304        LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_W::new(self, 28)
305    }
306    #[doc = "Bit 29 - Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
307    #[inline(always)]
308    #[must_use]
309    pub fn ledc_evt_duty_chng_end_ch1_st_clr(
310        &mut self,
311    ) -> LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_W<EVT_ST0_CLR_SPEC> {
312        LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_W::new(self, 29)
313    }
314    #[doc = "Bit 30 - Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
315    #[inline(always)]
316    #[must_use]
317    pub fn ledc_evt_duty_chng_end_ch2_st_clr(
318        &mut self,
319    ) -> LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_W<EVT_ST0_CLR_SPEC> {
320        LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_W::new(self, 30)
321    }
322    #[doc = "Bit 31 - Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
323    #[inline(always)]
324    #[must_use]
325    pub fn ledc_evt_duty_chng_end_ch3_st_clr(
326        &mut self,
327    ) -> LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_W<EVT_ST0_CLR_SPEC> {
328        LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_W::new(self, 31)
329    }
330}
331#[doc = "Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st0_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
332pub struct EVT_ST0_CLR_SPEC;
333impl crate::RegisterSpec for EVT_ST0_CLR_SPEC {
334    type Ux = u32;
335}
336#[doc = "`write(|w| ..)` method takes [`evt_st0_clr::W`](W) writer structure"]
337impl crate::Writable for EVT_ST0_CLR_SPEC {
338    type Safety = crate::Unsafe;
339    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
340    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
341}
342#[doc = "`reset()` method sets EVT_ST0_CLR to value 0"]
343impl crate::Resettable for EVT_ST0_CLR_SPEC {
344    const RESET_VALUE: u32 = 0;
345}
esp32p4/soc_etm/evt_st0_clr.rs

esp32p4/soc_etm/
evt_st0_clr.rs
