esp32p4/soc_etm/
ch_ena_ad1_clr.rs

1#[doc = "Register `CH_ENA_AD1_CLR` writer"]
2pub type W = crate::W<CH_ENA_AD1_CLR_SPEC>;
3#[doc = "Field `CH_CLR(32-49)` writer - Configures whether or not to clear ch%s enable.\\\\0: Invalid, No effect\\\\1: Clear"]
4pub type CH_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[cfg(feature = "impl-register-debug")]
6impl core::fmt::Debug for crate::generic::Reg<CH_ENA_AD1_CLR_SPEC> {
7    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
8        write!(f, "(not readable)")
9    }
10}
11impl W {
12    #[doc = "Configures whether or not to clear ch(32-49) enable.\\\\0: Invalid, No effect\\\\1: Clear"]
13    #[doc = ""]
14    #[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `CH_CLR32` field"]
15    #[inline(always)]
16    #[must_use]
17    pub fn ch_clr(&mut self, n: u8) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
18        #[allow(clippy::no_effect)]
19        [(); 18][n as usize];
20        CH_CLR_W::new(self, n)
21    }
22    #[doc = "Bit 0 - Configures whether or not to clear ch32 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
23    #[inline(always)]
24    #[must_use]
25    pub fn ch_clr32(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
26        CH_CLR_W::new(self, 0)
27    }
28    #[doc = "Bit 1 - Configures whether or not to clear ch33 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
29    #[inline(always)]
30    #[must_use]
31    pub fn ch_clr33(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
32        CH_CLR_W::new(self, 1)
33    }
34    #[doc = "Bit 2 - Configures whether or not to clear ch34 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
35    #[inline(always)]
36    #[must_use]
37    pub fn ch_clr34(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
38        CH_CLR_W::new(self, 2)
39    }
40    #[doc = "Bit 3 - Configures whether or not to clear ch35 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
41    #[inline(always)]
42    #[must_use]
43    pub fn ch_clr35(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
44        CH_CLR_W::new(self, 3)
45    }
46    #[doc = "Bit 4 - Configures whether or not to clear ch36 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
47    #[inline(always)]
48    #[must_use]
49    pub fn ch_clr36(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
50        CH_CLR_W::new(self, 4)
51    }
52    #[doc = "Bit 5 - Configures whether or not to clear ch37 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
53    #[inline(always)]
54    #[must_use]
55    pub fn ch_clr37(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
56        CH_CLR_W::new(self, 5)
57    }
58    #[doc = "Bit 6 - Configures whether or not to clear ch38 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
59    #[inline(always)]
60    #[must_use]
61    pub fn ch_clr38(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
62        CH_CLR_W::new(self, 6)
63    }
64    #[doc = "Bit 7 - Configures whether or not to clear ch39 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
65    #[inline(always)]
66    #[must_use]
67    pub fn ch_clr39(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
68        CH_CLR_W::new(self, 7)
69    }
70    #[doc = "Bit 8 - Configures whether or not to clear ch40 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
71    #[inline(always)]
72    #[must_use]
73    pub fn ch_clr40(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
74        CH_CLR_W::new(self, 8)
75    }
76    #[doc = "Bit 9 - Configures whether or not to clear ch41 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
77    #[inline(always)]
78    #[must_use]
79    pub fn ch_clr41(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
80        CH_CLR_W::new(self, 9)
81    }
82    #[doc = "Bit 10 - Configures whether or not to clear ch42 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
83    #[inline(always)]
84    #[must_use]
85    pub fn ch_clr42(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
86        CH_CLR_W::new(self, 10)
87    }
88    #[doc = "Bit 11 - Configures whether or not to clear ch43 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
89    #[inline(always)]
90    #[must_use]
91    pub fn ch_clr43(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
92        CH_CLR_W::new(self, 11)
93    }
94    #[doc = "Bit 12 - Configures whether or not to clear ch44 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
95    #[inline(always)]
96    #[must_use]
97    pub fn ch_clr44(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
98        CH_CLR_W::new(self, 12)
99    }
100    #[doc = "Bit 13 - Configures whether or not to clear ch45 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
101    #[inline(always)]
102    #[must_use]
103    pub fn ch_clr45(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
104        CH_CLR_W::new(self, 13)
105    }
106    #[doc = "Bit 14 - Configures whether or not to clear ch46 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
107    #[inline(always)]
108    #[must_use]
109    pub fn ch_clr46(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
110        CH_CLR_W::new(self, 14)
111    }
112    #[doc = "Bit 15 - Configures whether or not to clear ch47 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
113    #[inline(always)]
114    #[must_use]
115    pub fn ch_clr47(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
116        CH_CLR_W::new(self, 15)
117    }
118    #[doc = "Bit 16 - Configures whether or not to clear ch48 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
119    #[inline(always)]
120    #[must_use]
121    pub fn ch_clr48(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
122        CH_CLR_W::new(self, 16)
123    }
124    #[doc = "Bit 17 - Configures whether or not to clear ch49 enable.\\\\0: Invalid, No effect\\\\1: Clear"]
125    #[inline(always)]
126    #[must_use]
127    pub fn ch_clr49(&mut self) -> CH_CLR_W<CH_ENA_AD1_CLR_SPEC> {
128        CH_CLR_W::new(self, 17)
129    }
130}
131#[doc = "Channel enable clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ena_ad1_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
132pub struct CH_ENA_AD1_CLR_SPEC;
133impl crate::RegisterSpec for CH_ENA_AD1_CLR_SPEC {
134    type Ux = u32;
135}
136#[doc = "`write(|w| ..)` method takes [`ch_ena_ad1_clr::W`](W) writer structure"]
137impl crate::Writable for CH_ENA_AD1_CLR_SPEC {
138    type Safety = crate::Unsafe;
139    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
140    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
141}
142#[doc = "`reset()` method sets CH_ENA_AD1_CLR to value 0"]
143impl crate::Resettable for CH_ENA_AD1_CLR_SPEC {
144    const RESET_VALUE: u32 = 0;
145}
esp32p4/soc_etm/ch_ena_ad1_clr.rs

esp32p4/soc_etm/
ch_ena_ad1_clr.rs
