1#[doc = "Register `CLUT_CONF` reader"]
2pub type R = crate::R<CLUT_CONF_SPEC>;
3#[doc = "Register `CLUT_CONF` writer"]
4pub type W = crate::W<CLUT_CONF_SPEC>;
5#[doc = "Field `APB_FIFO_MASK` reader - 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr should be 01 to access sr clut and should be 10 to access blend0 clut and should be 11 to access blend 1 clut in memory mode."]
6pub type APB_FIFO_MASK_R = crate::BitReader;
7#[doc = "Field `APB_FIFO_MASK` writer - 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr should be 01 to access sr clut and should be 10 to access blend0 clut and should be 11 to access blend 1 clut in memory mode."]
8pub type APB_FIFO_MASK_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `BLEND0_CLUT_MEM_RST` reader - Write 1 then write 0 to this bit to reset BLEND0 CLUT."]
10pub type BLEND0_CLUT_MEM_RST_R = crate::BitReader;
11#[doc = "Field `BLEND0_CLUT_MEM_RST` writer - Write 1 then write 0 to this bit to reset BLEND0 CLUT."]
12pub type BLEND0_CLUT_MEM_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `BLEND1_CLUT_MEM_RST` reader - Write 1 then write 0 to this bit to reset BLEND1 CLUT."]
14pub type BLEND1_CLUT_MEM_RST_R = crate::BitReader;
15#[doc = "Field `BLEND1_CLUT_MEM_RST` writer - Write 1 then write 0 to this bit to reset BLEND1 CLUT."]
16pub type BLEND1_CLUT_MEM_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `BLEND0_CLUT_MEM_RDADDR_RST` reader - Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode."]
18pub type BLEND0_CLUT_MEM_RDADDR_RST_R = crate::BitReader;
19#[doc = "Field `BLEND0_CLUT_MEM_RDADDR_RST` writer - Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode."]
20pub type BLEND0_CLUT_MEM_RDADDR_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `BLEND1_CLUT_MEM_RDADDR_RST` reader - Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode."]
22pub type BLEND1_CLUT_MEM_RDADDR_RST_R = crate::BitReader;
23#[doc = "Field `BLEND1_CLUT_MEM_RDADDR_RST` writer - Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode."]
24pub type BLEND1_CLUT_MEM_RDADDR_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `BLEND0_CLUT_MEM_FORCE_PD` reader - 1: force power down BLEND CLUT memory."]
26pub type BLEND0_CLUT_MEM_FORCE_PD_R = crate::BitReader;
27#[doc = "Field `BLEND0_CLUT_MEM_FORCE_PD` writer - 1: force power down BLEND CLUT memory."]
28pub type BLEND0_CLUT_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `BLEND0_CLUT_MEM_FORCE_PU` reader - 1: force power up BLEND CLUT memory."]
30pub type BLEND0_CLUT_MEM_FORCE_PU_R = crate::BitReader;
31#[doc = "Field `BLEND0_CLUT_MEM_FORCE_PU` writer - 1: force power up BLEND CLUT memory."]
32pub type BLEND0_CLUT_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `BLEND0_CLUT_MEM_CLK_ENA` reader - 1: Force clock on for BLEND CLUT memory."]
34pub type BLEND0_CLUT_MEM_CLK_ENA_R = crate::BitReader;
35#[doc = "Field `BLEND0_CLUT_MEM_CLK_ENA` writer - 1: Force clock on for BLEND CLUT memory."]
36pub type BLEND0_CLUT_MEM_CLK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38 #[doc = "Bit 0 - 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr should be 01 to access sr clut and should be 10 to access blend0 clut and should be 11 to access blend 1 clut in memory mode."]
39 #[inline(always)]
40 pub fn apb_fifo_mask(&self) -> APB_FIFO_MASK_R {
41 APB_FIFO_MASK_R::new((self.bits & 1) != 0)
42 }
43 #[doc = "Bit 1 - Write 1 then write 0 to this bit to reset BLEND0 CLUT."]
44 #[inline(always)]
45 pub fn blend0_clut_mem_rst(&self) -> BLEND0_CLUT_MEM_RST_R {
46 BLEND0_CLUT_MEM_RST_R::new(((self.bits >> 1) & 1) != 0)
47 }
48 #[doc = "Bit 2 - Write 1 then write 0 to this bit to reset BLEND1 CLUT."]
49 #[inline(always)]
50 pub fn blend1_clut_mem_rst(&self) -> BLEND1_CLUT_MEM_RST_R {
51 BLEND1_CLUT_MEM_RST_R::new(((self.bits >> 2) & 1) != 0)
52 }
53 #[doc = "Bit 3 - Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode."]
54 #[inline(always)]
55 pub fn blend0_clut_mem_rdaddr_rst(&self) -> BLEND0_CLUT_MEM_RDADDR_RST_R {
56 BLEND0_CLUT_MEM_RDADDR_RST_R::new(((self.bits >> 3) & 1) != 0)
57 }
58 #[doc = "Bit 4 - Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode."]
59 #[inline(always)]
60 pub fn blend1_clut_mem_rdaddr_rst(&self) -> BLEND1_CLUT_MEM_RDADDR_RST_R {
61 BLEND1_CLUT_MEM_RDADDR_RST_R::new(((self.bits >> 4) & 1) != 0)
62 }
63 #[doc = "Bit 5 - 1: force power down BLEND CLUT memory."]
64 #[inline(always)]
65 pub fn blend0_clut_mem_force_pd(&self) -> BLEND0_CLUT_MEM_FORCE_PD_R {
66 BLEND0_CLUT_MEM_FORCE_PD_R::new(((self.bits >> 5) & 1) != 0)
67 }
68 #[doc = "Bit 6 - 1: force power up BLEND CLUT memory."]
69 #[inline(always)]
70 pub fn blend0_clut_mem_force_pu(&self) -> BLEND0_CLUT_MEM_FORCE_PU_R {
71 BLEND0_CLUT_MEM_FORCE_PU_R::new(((self.bits >> 6) & 1) != 0)
72 }
73 #[doc = "Bit 7 - 1: Force clock on for BLEND CLUT memory."]
74 #[inline(always)]
75 pub fn blend0_clut_mem_clk_ena(&self) -> BLEND0_CLUT_MEM_CLK_ENA_R {
76 BLEND0_CLUT_MEM_CLK_ENA_R::new(((self.bits >> 7) & 1) != 0)
77 }
78}
79#[cfg(feature = "impl-register-debug")]
80impl core::fmt::Debug for R {
81 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
82 f.debug_struct("CLUT_CONF")
83 .field(
84 "apb_fifo_mask",
85 &format_args!("{}", self.apb_fifo_mask().bit()),
86 )
87 .field(
88 "blend0_clut_mem_rst",
89 &format_args!("{}", self.blend0_clut_mem_rst().bit()),
90 )
91 .field(
92 "blend1_clut_mem_rst",
93 &format_args!("{}", self.blend1_clut_mem_rst().bit()),
94 )
95 .field(
96 "blend0_clut_mem_rdaddr_rst",
97 &format_args!("{}", self.blend0_clut_mem_rdaddr_rst().bit()),
98 )
99 .field(
100 "blend1_clut_mem_rdaddr_rst",
101 &format_args!("{}", self.blend1_clut_mem_rdaddr_rst().bit()),
102 )
103 .field(
104 "blend0_clut_mem_force_pd",
105 &format_args!("{}", self.blend0_clut_mem_force_pd().bit()),
106 )
107 .field(
108 "blend0_clut_mem_force_pu",
109 &format_args!("{}", self.blend0_clut_mem_force_pu().bit()),
110 )
111 .field(
112 "blend0_clut_mem_clk_ena",
113 &format_args!("{}", self.blend0_clut_mem_clk_ena().bit()),
114 )
115 .finish()
116 }
117}
118#[cfg(feature = "impl-register-debug")]
119impl core::fmt::Debug for crate::generic::Reg<CLUT_CONF_SPEC> {
120 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
121 core::fmt::Debug::fmt(&self.read(), f)
122 }
123}
124impl W {
125 #[doc = "Bit 0 - 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr should be 01 to access sr clut and should be 10 to access blend0 clut and should be 11 to access blend 1 clut in memory mode."]
126 #[inline(always)]
127 #[must_use]
128 pub fn apb_fifo_mask(&mut self) -> APB_FIFO_MASK_W<CLUT_CONF_SPEC> {
129 APB_FIFO_MASK_W::new(self, 0)
130 }
131 #[doc = "Bit 1 - Write 1 then write 0 to this bit to reset BLEND0 CLUT."]
132 #[inline(always)]
133 #[must_use]
134 pub fn blend0_clut_mem_rst(&mut self) -> BLEND0_CLUT_MEM_RST_W<CLUT_CONF_SPEC> {
135 BLEND0_CLUT_MEM_RST_W::new(self, 1)
136 }
137 #[doc = "Bit 2 - Write 1 then write 0 to this bit to reset BLEND1 CLUT."]
138 #[inline(always)]
139 #[must_use]
140 pub fn blend1_clut_mem_rst(&mut self) -> BLEND1_CLUT_MEM_RST_W<CLUT_CONF_SPEC> {
141 BLEND1_CLUT_MEM_RST_W::new(self, 2)
142 }
143 #[doc = "Bit 3 - Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode."]
144 #[inline(always)]
145 #[must_use]
146 pub fn blend0_clut_mem_rdaddr_rst(&mut self) -> BLEND0_CLUT_MEM_RDADDR_RST_W<CLUT_CONF_SPEC> {
147 BLEND0_CLUT_MEM_RDADDR_RST_W::new(self, 3)
148 }
149 #[doc = "Bit 4 - Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode."]
150 #[inline(always)]
151 #[must_use]
152 pub fn blend1_clut_mem_rdaddr_rst(&mut self) -> BLEND1_CLUT_MEM_RDADDR_RST_W<CLUT_CONF_SPEC> {
153 BLEND1_CLUT_MEM_RDADDR_RST_W::new(self, 4)
154 }
155 #[doc = "Bit 5 - 1: force power down BLEND CLUT memory."]
156 #[inline(always)]
157 #[must_use]
158 pub fn blend0_clut_mem_force_pd(&mut self) -> BLEND0_CLUT_MEM_FORCE_PD_W<CLUT_CONF_SPEC> {
159 BLEND0_CLUT_MEM_FORCE_PD_W::new(self, 5)
160 }
161 #[doc = "Bit 6 - 1: force power up BLEND CLUT memory."]
162 #[inline(always)]
163 #[must_use]
164 pub fn blend0_clut_mem_force_pu(&mut self) -> BLEND0_CLUT_MEM_FORCE_PU_W<CLUT_CONF_SPEC> {
165 BLEND0_CLUT_MEM_FORCE_PU_W::new(self, 6)
166 }
167 #[doc = "Bit 7 - 1: Force clock on for BLEND CLUT memory."]
168 #[inline(always)]
169 #[must_use]
170 pub fn blend0_clut_mem_clk_ena(&mut self) -> BLEND0_CLUT_MEM_CLK_ENA_W<CLUT_CONF_SPEC> {
171 BLEND0_CLUT_MEM_CLK_ENA_W::new(self, 7)
172 }
173}
174#[doc = "CLUT configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clut_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clut_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
175pub struct CLUT_CONF_SPEC;
176impl crate::RegisterSpec for CLUT_CONF_SPEC {
177 type Ux = u32;
178}
179#[doc = "`read()` method returns [`clut_conf::R`](R) reader structure"]
180impl crate::Readable for CLUT_CONF_SPEC {}
181#[doc = "`write(|w| ..)` method takes [`clut_conf::W`](W) writer structure"]
182impl crate::Writable for CLUT_CONF_SPEC {
183 type Safety = crate::Unsafe;
184 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
185 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
186}
187#[doc = "`reset()` method sets CLUT_CONF to value 0"]
188impl crate::Resettable for CLUT_CONF_SPEC {
189 const RESET_VALUE: u32 = 0;
190}