1#[doc = "Register `U%s_CONF0` reader"]
2pub type R = crate::R<U_CONF0_SPEC>;
3#[doc = "Register `U%s_CONF0` writer"]
4pub type W = crate::W<U_CONF0_SPEC>;
5#[doc = "Field `FILTER_THRES_U` reader - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
6pub type FILTER_THRES_U_R = crate::FieldReader<u16>;
7#[doc = "Field `FILTER_THRES_U` writer - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
8pub type FILTER_THRES_U_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
9#[doc = "Field `FILTER_EN_U` reader - This is the enable bit for unit %s's input filter."]
10pub type FILTER_EN_U_R = crate::BitReader;
11#[doc = "Field `FILTER_EN_U` writer - This is the enable bit for unit %s's input filter."]
12pub type FILTER_EN_U_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `THR_ZERO_EN_U` reader - This is the enable bit for unit %s's zero comparator."]
14pub type THR_ZERO_EN_U_R = crate::BitReader;
15#[doc = "Field `THR_ZERO_EN_U` writer - This is the enable bit for unit %s's zero comparator."]
16pub type THR_ZERO_EN_U_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `THR_H_LIM_EN_U` reader - This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt."]
18pub type THR_H_LIM_EN_U_R = crate::BitReader;
19#[doc = "Field `THR_H_LIM_EN_U` writer - This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt."]
20pub type THR_H_LIM_EN_U_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `THR_L_LIM_EN_U` reader - This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt."]
22pub type THR_L_LIM_EN_U_R = crate::BitReader;
23#[doc = "Field `THR_L_LIM_EN_U` writer - This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt."]
24pub type THR_L_LIM_EN_U_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `THR_THRES0_EN_U` reader - This is the enable bit for unit %s's thres0 comparator."]
26pub type THR_THRES0_EN_U_R = crate::BitReader;
27#[doc = "Field `THR_THRES0_EN_U` writer - This is the enable bit for unit %s's thres0 comparator."]
28pub type THR_THRES0_EN_U_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `THR_THRES1_EN_U` reader - This is the enable bit for unit %s's thres1 comparator."]
30pub type THR_THRES1_EN_U_R = crate::BitReader;
31#[doc = "Field `THR_THRES1_EN_U` writer - This is the enable bit for unit %s's thres1 comparator."]
32pub type THR_THRES1_EN_U_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CH0_NEG_MODE_U` reader - This register sets the behavior when the signal input of channel 0 detects a negative edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter"]
34pub type CH0_NEG_MODE_U_R = crate::FieldReader;
35#[doc = "Field `CH0_NEG_MODE_U` writer - This register sets the behavior when the signal input of channel 0 detects a negative edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter"]
36pub type CH0_NEG_MODE_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37#[doc = "Field `CH0_POS_MODE_U` reader - This register sets the behavior when the signal input of channel 0 detects a positive edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter"]
38pub type CH0_POS_MODE_U_R = crate::FieldReader;
39#[doc = "Field `CH0_POS_MODE_U` writer - This register sets the behavior when the signal input of channel 0 detects a positive edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter"]
40pub type CH0_POS_MODE_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
41#[doc = "Field `CH0_HCTRL_MODE_U` reader - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"]
42pub type CH0_HCTRL_MODE_U_R = crate::FieldReader;
43#[doc = "Field `CH0_HCTRL_MODE_U` writer - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"]
44pub type CH0_HCTRL_MODE_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
45#[doc = "Field `CH0_LCTRL_MODE_U` reader - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"]
46pub type CH0_LCTRL_MODE_U_R = crate::FieldReader;
47#[doc = "Field `CH0_LCTRL_MODE_U` writer - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"]
48pub type CH0_LCTRL_MODE_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
49#[doc = "Field `CH1_NEG_MODE_U` reader - This register sets the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter"]
50pub type CH1_NEG_MODE_U_R = crate::FieldReader;
51#[doc = "Field `CH1_NEG_MODE_U` writer - This register sets the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter"]
52pub type CH1_NEG_MODE_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
53#[doc = "Field `CH1_POS_MODE_U` reader - This register sets the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter"]
54pub type CH1_POS_MODE_U_R = crate::FieldReader;
55#[doc = "Field `CH1_POS_MODE_U` writer - This register sets the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter"]
56pub type CH1_POS_MODE_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
57#[doc = "Field `CH1_HCTRL_MODE_U` reader - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"]
58pub type CH1_HCTRL_MODE_U_R = crate::FieldReader;
59#[doc = "Field `CH1_HCTRL_MODE_U` writer - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"]
60pub type CH1_HCTRL_MODE_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
61#[doc = "Field `CH1_LCTRL_MODE_U` reader - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"]
62pub type CH1_LCTRL_MODE_U_R = crate::FieldReader;
63#[doc = "Field `CH1_LCTRL_MODE_U` writer - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"]
64pub type CH1_LCTRL_MODE_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
65impl R {
66 #[doc = "Bits 0:9 - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
67 #[inline(always)]
68 pub fn filter_thres_u(&self) -> FILTER_THRES_U_R {
69 FILTER_THRES_U_R::new((self.bits & 0x03ff) as u16)
70 }
71 #[doc = "Bit 10 - This is the enable bit for unit %s's input filter."]
72 #[inline(always)]
73 pub fn filter_en_u(&self) -> FILTER_EN_U_R {
74 FILTER_EN_U_R::new(((self.bits >> 10) & 1) != 0)
75 }
76 #[doc = "Bit 11 - This is the enable bit for unit %s's zero comparator."]
77 #[inline(always)]
78 pub fn thr_zero_en_u(&self) -> THR_ZERO_EN_U_R {
79 THR_ZERO_EN_U_R::new(((self.bits >> 11) & 1) != 0)
80 }
81 #[doc = "Bit 12 - This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt."]
82 #[inline(always)]
83 pub fn thr_h_lim_en_u(&self) -> THR_H_LIM_EN_U_R {
84 THR_H_LIM_EN_U_R::new(((self.bits >> 12) & 1) != 0)
85 }
86 #[doc = "Bit 13 - This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt."]
87 #[inline(always)]
88 pub fn thr_l_lim_en_u(&self) -> THR_L_LIM_EN_U_R {
89 THR_L_LIM_EN_U_R::new(((self.bits >> 13) & 1) != 0)
90 }
91 #[doc = "Bit 14 - This is the enable bit for unit %s's thres0 comparator."]
92 #[inline(always)]
93 pub fn thr_thres0_en_u(&self) -> THR_THRES0_EN_U_R {
94 THR_THRES0_EN_U_R::new(((self.bits >> 14) & 1) != 0)
95 }
96 #[doc = "Bit 15 - This is the enable bit for unit %s's thres1 comparator."]
97 #[inline(always)]
98 pub fn thr_thres1_en_u(&self) -> THR_THRES1_EN_U_R {
99 THR_THRES1_EN_U_R::new(((self.bits >> 15) & 1) != 0)
100 }
101 #[doc = "Bits 16:17 - This register sets the behavior when the signal input of channel 0 detects a negative edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter"]
102 #[inline(always)]
103 pub fn ch0_neg_mode_u(&self) -> CH0_NEG_MODE_U_R {
104 CH0_NEG_MODE_U_R::new(((self.bits >> 16) & 3) as u8)
105 }
106 #[doc = "Bits 18:19 - This register sets the behavior when the signal input of channel 0 detects a positive edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter"]
107 #[inline(always)]
108 pub fn ch0_pos_mode_u(&self) -> CH0_POS_MODE_U_R {
109 CH0_POS_MODE_U_R::new(((self.bits >> 18) & 3) as u8)
110 }
111 #[doc = "Bits 20:21 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"]
112 #[inline(always)]
113 pub fn ch0_hctrl_mode_u(&self) -> CH0_HCTRL_MODE_U_R {
114 CH0_HCTRL_MODE_U_R::new(((self.bits >> 20) & 3) as u8)
115 }
116 #[doc = "Bits 22:23 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"]
117 #[inline(always)]
118 pub fn ch0_lctrl_mode_u(&self) -> CH0_LCTRL_MODE_U_R {
119 CH0_LCTRL_MODE_U_R::new(((self.bits >> 22) & 3) as u8)
120 }
121 #[doc = "Bits 24:25 - This register sets the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter"]
122 #[inline(always)]
123 pub fn ch1_neg_mode_u(&self) -> CH1_NEG_MODE_U_R {
124 CH1_NEG_MODE_U_R::new(((self.bits >> 24) & 3) as u8)
125 }
126 #[doc = "Bits 26:27 - This register sets the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter"]
127 #[inline(always)]
128 pub fn ch1_pos_mode_u(&self) -> CH1_POS_MODE_U_R {
129 CH1_POS_MODE_U_R::new(((self.bits >> 26) & 3) as u8)
130 }
131 #[doc = "Bits 28:29 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"]
132 #[inline(always)]
133 pub fn ch1_hctrl_mode_u(&self) -> CH1_HCTRL_MODE_U_R {
134 CH1_HCTRL_MODE_U_R::new(((self.bits >> 28) & 3) as u8)
135 }
136 #[doc = "Bits 30:31 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"]
137 #[inline(always)]
138 pub fn ch1_lctrl_mode_u(&self) -> CH1_LCTRL_MODE_U_R {
139 CH1_LCTRL_MODE_U_R::new(((self.bits >> 30) & 3) as u8)
140 }
141}
142#[cfg(feature = "impl-register-debug")]
143impl core::fmt::Debug for R {
144 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
145 f.debug_struct("U_CONF0")
146 .field(
147 "filter_thres_u",
148 &format_args!("{}", self.filter_thres_u().bits()),
149 )
150 .field("filter_en_u", &format_args!("{}", self.filter_en_u().bit()))
151 .field(
152 "thr_zero_en_u",
153 &format_args!("{}", self.thr_zero_en_u().bit()),
154 )
155 .field(
156 "thr_h_lim_en_u",
157 &format_args!("{}", self.thr_h_lim_en_u().bit()),
158 )
159 .field(
160 "thr_l_lim_en_u",
161 &format_args!("{}", self.thr_l_lim_en_u().bit()),
162 )
163 .field(
164 "thr_thres0_en_u",
165 &format_args!("{}", self.thr_thres0_en_u().bit()),
166 )
167 .field(
168 "thr_thres1_en_u",
169 &format_args!("{}", self.thr_thres1_en_u().bit()),
170 )
171 .field(
172 "ch0_neg_mode_u",
173 &format_args!("{}", self.ch0_neg_mode_u().bits()),
174 )
175 .field(
176 "ch0_pos_mode_u",
177 &format_args!("{}", self.ch0_pos_mode_u().bits()),
178 )
179 .field(
180 "ch0_hctrl_mode_u",
181 &format_args!("{}", self.ch0_hctrl_mode_u().bits()),
182 )
183 .field(
184 "ch0_lctrl_mode_u",
185 &format_args!("{}", self.ch0_lctrl_mode_u().bits()),
186 )
187 .field(
188 "ch1_neg_mode_u",
189 &format_args!("{}", self.ch1_neg_mode_u().bits()),
190 )
191 .field(
192 "ch1_pos_mode_u",
193 &format_args!("{}", self.ch1_pos_mode_u().bits()),
194 )
195 .field(
196 "ch1_hctrl_mode_u",
197 &format_args!("{}", self.ch1_hctrl_mode_u().bits()),
198 )
199 .field(
200 "ch1_lctrl_mode_u",
201 &format_args!("{}", self.ch1_lctrl_mode_u().bits()),
202 )
203 .finish()
204 }
205}
206#[cfg(feature = "impl-register-debug")]
207impl core::fmt::Debug for crate::generic::Reg<U_CONF0_SPEC> {
208 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
209 core::fmt::Debug::fmt(&self.read(), f)
210 }
211}
212impl W {
213 #[doc = "Bits 0:9 - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
214 #[inline(always)]
215 #[must_use]
216 pub fn filter_thres_u(&mut self) -> FILTER_THRES_U_W<U_CONF0_SPEC> {
217 FILTER_THRES_U_W::new(self, 0)
218 }
219 #[doc = "Bit 10 - This is the enable bit for unit %s's input filter."]
220 #[inline(always)]
221 #[must_use]
222 pub fn filter_en_u(&mut self) -> FILTER_EN_U_W<U_CONF0_SPEC> {
223 FILTER_EN_U_W::new(self, 10)
224 }
225 #[doc = "Bit 11 - This is the enable bit for unit %s's zero comparator."]
226 #[inline(always)]
227 #[must_use]
228 pub fn thr_zero_en_u(&mut self) -> THR_ZERO_EN_U_W<U_CONF0_SPEC> {
229 THR_ZERO_EN_U_W::new(self, 11)
230 }
231 #[doc = "Bit 12 - This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt."]
232 #[inline(always)]
233 #[must_use]
234 pub fn thr_h_lim_en_u(&mut self) -> THR_H_LIM_EN_U_W<U_CONF0_SPEC> {
235 THR_H_LIM_EN_U_W::new(self, 12)
236 }
237 #[doc = "Bit 13 - This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt."]
238 #[inline(always)]
239 #[must_use]
240 pub fn thr_l_lim_en_u(&mut self) -> THR_L_LIM_EN_U_W<U_CONF0_SPEC> {
241 THR_L_LIM_EN_U_W::new(self, 13)
242 }
243 #[doc = "Bit 14 - This is the enable bit for unit %s's thres0 comparator."]
244 #[inline(always)]
245 #[must_use]
246 pub fn thr_thres0_en_u(&mut self) -> THR_THRES0_EN_U_W<U_CONF0_SPEC> {
247 THR_THRES0_EN_U_W::new(self, 14)
248 }
249 #[doc = "Bit 15 - This is the enable bit for unit %s's thres1 comparator."]
250 #[inline(always)]
251 #[must_use]
252 pub fn thr_thres1_en_u(&mut self) -> THR_THRES1_EN_U_W<U_CONF0_SPEC> {
253 THR_THRES1_EN_U_W::new(self, 15)
254 }
255 #[doc = "Bits 16:17 - This register sets the behavior when the signal input of channel 0 detects a negative edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter"]
256 #[inline(always)]
257 #[must_use]
258 pub fn ch0_neg_mode_u(&mut self) -> CH0_NEG_MODE_U_W<U_CONF0_SPEC> {
259 CH0_NEG_MODE_U_W::new(self, 16)
260 }
261 #[doc = "Bits 18:19 - This register sets the behavior when the signal input of channel 0 detects a positive edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter"]
262 #[inline(always)]
263 #[must_use]
264 pub fn ch0_pos_mode_u(&mut self) -> CH0_POS_MODE_U_W<U_CONF0_SPEC> {
265 CH0_POS_MODE_U_W::new(self, 18)
266 }
267 #[doc = "Bits 20:21 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"]
268 #[inline(always)]
269 #[must_use]
270 pub fn ch0_hctrl_mode_u(&mut self) -> CH0_HCTRL_MODE_U_W<U_CONF0_SPEC> {
271 CH0_HCTRL_MODE_U_W::new(self, 20)
272 }
273 #[doc = "Bits 22:23 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"]
274 #[inline(always)]
275 #[must_use]
276 pub fn ch0_lctrl_mode_u(&mut self) -> CH0_LCTRL_MODE_U_W<U_CONF0_SPEC> {
277 CH0_LCTRL_MODE_U_W::new(self, 22)
278 }
279 #[doc = "Bits 24:25 - This register sets the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter"]
280 #[inline(always)]
281 #[must_use]
282 pub fn ch1_neg_mode_u(&mut self) -> CH1_NEG_MODE_U_W<U_CONF0_SPEC> {
283 CH1_NEG_MODE_U_W::new(self, 24)
284 }
285 #[doc = "Bits 26:27 - This register sets the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter"]
286 #[inline(always)]
287 #[must_use]
288 pub fn ch1_pos_mode_u(&mut self) -> CH1_POS_MODE_U_W<U_CONF0_SPEC> {
289 CH1_POS_MODE_U_W::new(self, 26)
290 }
291 #[doc = "Bits 28:29 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"]
292 #[inline(always)]
293 #[must_use]
294 pub fn ch1_hctrl_mode_u(&mut self) -> CH1_HCTRL_MODE_U_W<U_CONF0_SPEC> {
295 CH1_HCTRL_MODE_U_W::new(self, 28)
296 }
297 #[doc = "Bits 30:31 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"]
298 #[inline(always)]
299 #[must_use]
300 pub fn ch1_lctrl_mode_u(&mut self) -> CH1_LCTRL_MODE_U_W<U_CONF0_SPEC> {
301 CH1_LCTRL_MODE_U_W::new(self, 30)
302 }
303}
304#[doc = "Configuration register 0 for unit %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_conf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u_conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
305pub struct U_CONF0_SPEC;
306impl crate::RegisterSpec for U_CONF0_SPEC {
307 type Ux = u32;
308}
309#[doc = "`read()` method returns [`u_conf0::R`](R) reader structure"]
310impl crate::Readable for U_CONF0_SPEC {}
311#[doc = "`write(|w| ..)` method takes [`u_conf0::W`](W) writer structure"]
312impl crate::Writable for U_CONF0_SPEC {
313 type Safety = crate::Unsafe;
314 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
315 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
316}
317#[doc = "`reset()` method sets U%s_CONF0 to value 0x3c10"]
318impl crate::Resettable for U_CONF0_SPEC {
319 const RESET_VALUE: u32 = 0x3c10;
320}