esp32p4/mipi_dsi_bridge/
mem_clk_ctrl.rs

1#[doc = "Register `MEM_CLK_CTRL` reader"]
2pub type R = crate::R<MEM_CLK_CTRL_SPEC>;
3#[doc = "Register `MEM_CLK_CTRL` writer"]
4pub type W = crate::W<MEM_CLK_CTRL_SPEC>;
5#[doc = "Field `DSI_BRIDGE_MEM_CLK_FORCE_ON` reader - this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: force on"]
6pub type DSI_BRIDGE_MEM_CLK_FORCE_ON_R = crate::BitReader;
7#[doc = "Field `DSI_BRIDGE_MEM_CLK_FORCE_ON` writer - this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: force on"]
8pub type DSI_BRIDGE_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DSI_MEM_CLK_FORCE_ON` reader - this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on"]
10pub type DSI_MEM_CLK_FORCE_ON_R = crate::BitReader;
11#[doc = "Field `DSI_MEM_CLK_FORCE_ON` writer - this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on"]
12pub type DSI_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bit 0 - this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: force on"]
15    #[inline(always)]
16    pub fn dsi_bridge_mem_clk_force_on(&self) -> DSI_BRIDGE_MEM_CLK_FORCE_ON_R {
17        DSI_BRIDGE_MEM_CLK_FORCE_ON_R::new((self.bits & 1) != 0)
18    }
19    #[doc = "Bit 1 - this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on"]
20    #[inline(always)]
21    pub fn dsi_mem_clk_force_on(&self) -> DSI_MEM_CLK_FORCE_ON_R {
22        DSI_MEM_CLK_FORCE_ON_R::new(((self.bits >> 1) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("MEM_CLK_CTRL")
29            .field(
30                "dsi_bridge_mem_clk_force_on",
31                &format_args!("{}", self.dsi_bridge_mem_clk_force_on().bit()),
32            )
33            .field(
34                "dsi_mem_clk_force_on",
35                &format_args!("{}", self.dsi_mem_clk_force_on().bit()),
36            )
37            .finish()
38    }
39}
40#[cfg(feature = "impl-register-debug")]
41impl core::fmt::Debug for crate::generic::Reg<MEM_CLK_CTRL_SPEC> {
42    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
43        core::fmt::Debug::fmt(&self.read(), f)
44    }
45}
46impl W {
47    #[doc = "Bit 0 - this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: force on"]
48    #[inline(always)]
49    #[must_use]
50    pub fn dsi_bridge_mem_clk_force_on(
51        &mut self,
52    ) -> DSI_BRIDGE_MEM_CLK_FORCE_ON_W<MEM_CLK_CTRL_SPEC> {
53        DSI_BRIDGE_MEM_CLK_FORCE_ON_W::new(self, 0)
54    }
55    #[doc = "Bit 1 - this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on"]
56    #[inline(always)]
57    #[must_use]
58    pub fn dsi_mem_clk_force_on(&mut self) -> DSI_MEM_CLK_FORCE_ON_W<MEM_CLK_CTRL_SPEC> {
59        DSI_MEM_CLK_FORCE_ON_W::new(self, 1)
60    }
61}
62#[doc = "dsi_bridge mem force on control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_clk_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_clk_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
63pub struct MEM_CLK_CTRL_SPEC;
64impl crate::RegisterSpec for MEM_CLK_CTRL_SPEC {
65    type Ux = u32;
66}
67#[doc = "`read()` method returns [`mem_clk_ctrl::R`](R) reader structure"]
68impl crate::Readable for MEM_CLK_CTRL_SPEC {}
69#[doc = "`write(|w| ..)` method takes [`mem_clk_ctrl::W`](W) writer structure"]
70impl crate::Writable for MEM_CLK_CTRL_SPEC {
71    type Safety = crate::Unsafe;
72    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
73    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
74}
75#[doc = "`reset()` method sets MEM_CLK_CTRL to value 0"]
76impl crate::Resettable for MEM_CLK_CTRL_SPEC {
77    const RESET_VALUE: u32 = 0;
78}
esp32p4/mipi_dsi_bridge/mem_clk_ctrl.rs

esp32p4/mipi_dsi_bridge/
mem_clk_ctrl.rs
