esp32p4/mipi_csi_bridge/
mem_ctrl.rs

1#[doc = "Register `MEM_CTRL` reader"]
2pub type R = crate::R<MEM_CTRL_SPEC>;
3#[doc = "Register `MEM_CTRL` writer"]
4pub type W = crate::W<MEM_CTRL_SPEC>;
5#[doc = "Field `CSI_BRIDGE_MEM_CLK_FORCE_ON` reader - csi bridge memory clock gating force on."]
6pub type CSI_BRIDGE_MEM_CLK_FORCE_ON_R = crate::BitReader;
7#[doc = "Field `CSI_BRIDGE_MEM_CLK_FORCE_ON` writer - csi bridge memory clock gating force on."]
8pub type CSI_BRIDGE_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CSI_MEM_AUX_CTRL` reader - N/A"]
10pub type CSI_MEM_AUX_CTRL_R = crate::FieldReader<u16>;
11#[doc = "Field `CSI_MEM_AUX_CTRL` writer - N/A"]
12pub type CSI_MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
13impl R {
14    #[doc = "Bit 0 - csi bridge memory clock gating force on."]
15    #[inline(always)]
16    pub fn csi_bridge_mem_clk_force_on(&self) -> CSI_BRIDGE_MEM_CLK_FORCE_ON_R {
17        CSI_BRIDGE_MEM_CLK_FORCE_ON_R::new((self.bits & 1) != 0)
18    }
19    #[doc = "Bits 1:14 - N/A"]
20    #[inline(always)]
21    pub fn csi_mem_aux_ctrl(&self) -> CSI_MEM_AUX_CTRL_R {
22        CSI_MEM_AUX_CTRL_R::new(((self.bits >> 1) & 0x3fff) as u16)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("MEM_CTRL")
29            .field(
30                "csi_bridge_mem_clk_force_on",
31                &format_args!("{}", self.csi_bridge_mem_clk_force_on().bit()),
32            )
33            .field(
34                "csi_mem_aux_ctrl",
35                &format_args!("{}", self.csi_mem_aux_ctrl().bits()),
36            )
37            .finish()
38    }
39}
40#[cfg(feature = "impl-register-debug")]
41impl core::fmt::Debug for crate::generic::Reg<MEM_CTRL_SPEC> {
42    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
43        core::fmt::Debug::fmt(&self.read(), f)
44    }
45}
46impl W {
47    #[doc = "Bit 0 - csi bridge memory clock gating force on."]
48    #[inline(always)]
49    #[must_use]
50    pub fn csi_bridge_mem_clk_force_on(&mut self) -> CSI_BRIDGE_MEM_CLK_FORCE_ON_W<MEM_CTRL_SPEC> {
51        CSI_BRIDGE_MEM_CLK_FORCE_ON_W::new(self, 0)
52    }
53    #[doc = "Bits 1:14 - N/A"]
54    #[inline(always)]
55    #[must_use]
56    pub fn csi_mem_aux_ctrl(&mut self) -> CSI_MEM_AUX_CTRL_W<MEM_CTRL_SPEC> {
57        CSI_MEM_AUX_CTRL_W::new(self, 1)
58    }
59}
60#[doc = "csi bridge buffer control.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
61pub struct MEM_CTRL_SPEC;
62impl crate::RegisterSpec for MEM_CTRL_SPEC {
63    type Ux = u32;
64}
65#[doc = "`read()` method returns [`mem_ctrl::R`](R) reader structure"]
66impl crate::Readable for MEM_CTRL_SPEC {}
67#[doc = "`write(|w| ..)` method takes [`mem_ctrl::W`](W) writer structure"]
68impl crate::Writable for MEM_CTRL_SPEC {
69    type Safety = crate::Unsafe;
70    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
71    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72}
73#[doc = "`reset()` method sets MEM_CTRL to value 0x2640"]
74impl crate::Resettable for MEM_CTRL_SPEC {
75    const RESET_VALUE: u32 = 0x2640;
76}
esp32p4/mipi_csi_bridge/mem_ctrl.rs

esp32p4/mipi_csi_bridge/
mem_ctrl.rs
