esp32p4/mcpwm0/
cap_timer_phase.rs

1#[doc = "Register `CAP_TIMER_PHASE` reader"]
2pub type R = crate::R<CAP_TIMER_PHASE_SPEC>;
3#[doc = "Register `CAP_TIMER_PHASE` writer"]
4pub type W = crate::W<CAP_TIMER_PHASE_SPEC>;
5#[doc = "Field `CAP_PHASE` reader - Configures phase value for capture timer sync operation."]
6pub type CAP_PHASE_R = crate::FieldReader<u32>;
7#[doc = "Field `CAP_PHASE` writer - Configures phase value for capture timer sync operation."]
8pub type CAP_PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    #[doc = "Bits 0:31 - Configures phase value for capture timer sync operation."]
11    #[inline(always)]
12    pub fn cap_phase(&self) -> CAP_PHASE_R {
13        CAP_PHASE_R::new(self.bits)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("CAP_TIMER_PHASE")
20            .field("cap_phase", &format_args!("{}", self.cap_phase().bits()))
21            .finish()
22    }
23}
24#[cfg(feature = "impl-register-debug")]
25impl core::fmt::Debug for crate::generic::Reg<CAP_TIMER_PHASE_SPEC> {
26    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
27        core::fmt::Debug::fmt(&self.read(), f)
28    }
29}
30impl W {
31    #[doc = "Bits 0:31 - Configures phase value for capture timer sync operation."]
32    #[inline(always)]
33    #[must_use]
34    pub fn cap_phase(&mut self) -> CAP_PHASE_W<CAP_TIMER_PHASE_SPEC> {
35        CAP_PHASE_W::new(self, 0)
36    }
37}
38#[doc = "Capture timer sync phase register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_timer_phase::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cap_timer_phase::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
39pub struct CAP_TIMER_PHASE_SPEC;
40impl crate::RegisterSpec for CAP_TIMER_PHASE_SPEC {
41    type Ux = u32;
42}
43#[doc = "`read()` method returns [`cap_timer_phase::R`](R) reader structure"]
44impl crate::Readable for CAP_TIMER_PHASE_SPEC {}
45#[doc = "`write(|w| ..)` method takes [`cap_timer_phase::W`](W) writer structure"]
46impl crate::Writable for CAP_TIMER_PHASE_SPEC {
47    type Safety = crate::Unsafe;
48    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
49    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
50}
51#[doc = "`reset()` method sets CAP_TIMER_PHASE to value 0"]
52impl crate::Resettable for CAP_TIMER_PHASE_SPEC {
53    const RESET_VALUE: u32 = 0;
54}
esp32p4/mcpwm0/cap_timer_phase.rs

esp32p4/mcpwm0/
cap_timer_phase.rs
