esp32p4/lp_adc/
meas2_ctrl1.rs1#[doc = "Register `MEAS2_CTRL1` reader"]
2pub type R = crate::R<MEAS2_CTRL1_SPEC>;
3#[doc = "Register `MEAS2_CTRL1` writer"]
4pub type W = crate::W<MEAS2_CTRL1_SPEC>;
5#[doc = "Field `SAR2_CNTL_STATE` reader - saradc2_cntl_fsm."]
6pub type SAR2_CNTL_STATE_R = crate::FieldReader;
7#[doc = "Field `SAR2_PWDET_CAL_EN` reader - RTC control pwdet enable."]
8pub type SAR2_PWDET_CAL_EN_R = crate::BitReader;
9#[doc = "Field `SAR2_PWDET_CAL_EN` writer - RTC control pwdet enable."]
10pub type SAR2_PWDET_CAL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `SAR2_PKDET_CAL_EN` reader - RTC control pkdet enable."]
12pub type SAR2_PKDET_CAL_EN_R = crate::BitReader;
13#[doc = "Field `SAR2_PKDET_CAL_EN` writer - RTC control pkdet enable."]
14pub type SAR2_PKDET_CAL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `SAR2_EN_TEST` reader - SAR2_EN_TEST."]
16pub type SAR2_EN_TEST_R = crate::BitReader;
17#[doc = "Field `SAR2_EN_TEST` writer - SAR2_EN_TEST."]
18pub type SAR2_EN_TEST_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `SAR2_RSTB_FORCE` reader - N/A"]
20pub type SAR2_RSTB_FORCE_R = crate::FieldReader;
21#[doc = "Field `SAR2_RSTB_FORCE` writer - N/A"]
22pub type SAR2_RSTB_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
23#[doc = "Field `SAR2_STANDBY_WAIT` reader - N/A"]
24pub type SAR2_STANDBY_WAIT_R = crate::FieldReader;
25#[doc = "Field `SAR2_STANDBY_WAIT` writer - N/A"]
26pub type SAR2_STANDBY_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
27#[doc = "Field `SAR2_RSTB_WAIT` reader - N/A"]
28pub type SAR2_RSTB_WAIT_R = crate::FieldReader;
29#[doc = "Field `SAR2_RSTB_WAIT` writer - N/A"]
30pub type SAR2_RSTB_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
31#[doc = "Field `SAR2_XPD_WAIT` reader - N/A"]
32pub type SAR2_XPD_WAIT_R = crate::FieldReader;
33#[doc = "Field `SAR2_XPD_WAIT` writer - N/A"]
34pub type SAR2_XPD_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
35impl R {
36 #[doc = "Bits 0:2 - saradc2_cntl_fsm."]
37 #[inline(always)]
38 pub fn sar2_cntl_state(&self) -> SAR2_CNTL_STATE_R {
39 SAR2_CNTL_STATE_R::new((self.bits & 7) as u8)
40 }
41 #[doc = "Bit 3 - RTC control pwdet enable."]
42 #[inline(always)]
43 pub fn sar2_pwdet_cal_en(&self) -> SAR2_PWDET_CAL_EN_R {
44 SAR2_PWDET_CAL_EN_R::new(((self.bits >> 3) & 1) != 0)
45 }
46 #[doc = "Bit 4 - RTC control pkdet enable."]
47 #[inline(always)]
48 pub fn sar2_pkdet_cal_en(&self) -> SAR2_PKDET_CAL_EN_R {
49 SAR2_PKDET_CAL_EN_R::new(((self.bits >> 4) & 1) != 0)
50 }
51 #[doc = "Bit 5 - SAR2_EN_TEST."]
52 #[inline(always)]
53 pub fn sar2_en_test(&self) -> SAR2_EN_TEST_R {
54 SAR2_EN_TEST_R::new(((self.bits >> 5) & 1) != 0)
55 }
56 #[doc = "Bits 6:7 - N/A"]
57 #[inline(always)]
58 pub fn sar2_rstb_force(&self) -> SAR2_RSTB_FORCE_R {
59 SAR2_RSTB_FORCE_R::new(((self.bits >> 6) & 3) as u8)
60 }
61 #[doc = "Bits 8:15 - N/A"]
62 #[inline(always)]
63 pub fn sar2_standby_wait(&self) -> SAR2_STANDBY_WAIT_R {
64 SAR2_STANDBY_WAIT_R::new(((self.bits >> 8) & 0xff) as u8)
65 }
66 #[doc = "Bits 16:23 - N/A"]
67 #[inline(always)]
68 pub fn sar2_rstb_wait(&self) -> SAR2_RSTB_WAIT_R {
69 SAR2_RSTB_WAIT_R::new(((self.bits >> 16) & 0xff) as u8)
70 }
71 #[doc = "Bits 24:31 - N/A"]
72 #[inline(always)]
73 pub fn sar2_xpd_wait(&self) -> SAR2_XPD_WAIT_R {
74 SAR2_XPD_WAIT_R::new(((self.bits >> 24) & 0xff) as u8)
75 }
76}
77#[cfg(feature = "impl-register-debug")]
78impl core::fmt::Debug for R {
79 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
80 f.debug_struct("MEAS2_CTRL1")
81 .field(
82 "sar2_cntl_state",
83 &format_args!("{}", self.sar2_cntl_state().bits()),
84 )
85 .field(
86 "sar2_pwdet_cal_en",
87 &format_args!("{}", self.sar2_pwdet_cal_en().bit()),
88 )
89 .field(
90 "sar2_pkdet_cal_en",
91 &format_args!("{}", self.sar2_pkdet_cal_en().bit()),
92 )
93 .field(
94 "sar2_en_test",
95 &format_args!("{}", self.sar2_en_test().bit()),
96 )
97 .field(
98 "sar2_rstb_force",
99 &format_args!("{}", self.sar2_rstb_force().bits()),
100 )
101 .field(
102 "sar2_standby_wait",
103 &format_args!("{}", self.sar2_standby_wait().bits()),
104 )
105 .field(
106 "sar2_rstb_wait",
107 &format_args!("{}", self.sar2_rstb_wait().bits()),
108 )
109 .field(
110 "sar2_xpd_wait",
111 &format_args!("{}", self.sar2_xpd_wait().bits()),
112 )
113 .finish()
114 }
115}
116#[cfg(feature = "impl-register-debug")]
117impl core::fmt::Debug for crate::generic::Reg<MEAS2_CTRL1_SPEC> {
118 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
119 core::fmt::Debug::fmt(&self.read(), f)
120 }
121}
122impl W {
123 #[doc = "Bit 3 - RTC control pwdet enable."]
124 #[inline(always)]
125 #[must_use]
126 pub fn sar2_pwdet_cal_en(&mut self) -> SAR2_PWDET_CAL_EN_W<MEAS2_CTRL1_SPEC> {
127 SAR2_PWDET_CAL_EN_W::new(self, 3)
128 }
129 #[doc = "Bit 4 - RTC control pkdet enable."]
130 #[inline(always)]
131 #[must_use]
132 pub fn sar2_pkdet_cal_en(&mut self) -> SAR2_PKDET_CAL_EN_W<MEAS2_CTRL1_SPEC> {
133 SAR2_PKDET_CAL_EN_W::new(self, 4)
134 }
135 #[doc = "Bit 5 - SAR2_EN_TEST."]
136 #[inline(always)]
137 #[must_use]
138 pub fn sar2_en_test(&mut self) -> SAR2_EN_TEST_W<MEAS2_CTRL1_SPEC> {
139 SAR2_EN_TEST_W::new(self, 5)
140 }
141 #[doc = "Bits 6:7 - N/A"]
142 #[inline(always)]
143 #[must_use]
144 pub fn sar2_rstb_force(&mut self) -> SAR2_RSTB_FORCE_W<MEAS2_CTRL1_SPEC> {
145 SAR2_RSTB_FORCE_W::new(self, 6)
146 }
147 #[doc = "Bits 8:15 - N/A"]
148 #[inline(always)]
149 #[must_use]
150 pub fn sar2_standby_wait(&mut self) -> SAR2_STANDBY_WAIT_W<MEAS2_CTRL1_SPEC> {
151 SAR2_STANDBY_WAIT_W::new(self, 8)
152 }
153 #[doc = "Bits 16:23 - N/A"]
154 #[inline(always)]
155 #[must_use]
156 pub fn sar2_rstb_wait(&mut self) -> SAR2_RSTB_WAIT_W<MEAS2_CTRL1_SPEC> {
157 SAR2_RSTB_WAIT_W::new(self, 16)
158 }
159 #[doc = "Bits 24:31 - N/A"]
160 #[inline(always)]
161 #[must_use]
162 pub fn sar2_xpd_wait(&mut self) -> SAR2_XPD_WAIT_W<MEAS2_CTRL1_SPEC> {
163 SAR2_XPD_WAIT_W::new(self, 24)
164 }
165}
166#[doc = "ADC2 configuration registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`meas2_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`meas2_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
167pub struct MEAS2_CTRL1_SPEC;
168impl crate::RegisterSpec for MEAS2_CTRL1_SPEC {
169 type Ux = u32;
170}
171#[doc = "`read()` method returns [`meas2_ctrl1::R`](R) reader structure"]
172impl crate::Readable for MEAS2_CTRL1_SPEC {}
173#[doc = "`write(|w| ..)` method takes [`meas2_ctrl1::W`](W) writer structure"]
174impl crate::Writable for MEAS2_CTRL1_SPEC {
175 type Safety = crate::Unsafe;
176 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
177 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
178}
179#[doc = "`reset()` method sets MEAS2_CTRL1 to value 0x0702_0200"]
180impl crate::Resettable for MEAS2_CTRL1_SPEC {
181 const RESET_VALUE: u32 = 0x0702_0200;
182}