1#[doc = "Register `INT_ST_ENA` reader"]
2pub type R = crate::R<INT_ST_ENA_SPEC>;
3#[doc = "Register `INT_ST_ENA` writer"]
4pub type W = crate::W<INT_ST_ENA_SPEC>;
5#[doc = "Field `TX_DATA_BUF_THLD_INT_ENA` reader - Transmit Buffer threshold status enable."]
6pub type TX_DATA_BUF_THLD_INT_ENA_R = crate::BitReader;
7#[doc = "Field `TX_DATA_BUF_THLD_INT_ENA` writer - Transmit Buffer threshold status enable."]
8pub type TX_DATA_BUF_THLD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `RX_DATA_BUF_THLD_INT_ENA` reader - Receive Buffer threshold status enable."]
10pub type RX_DATA_BUF_THLD_INT_ENA_R = crate::BitReader;
11#[doc = "Field `RX_DATA_BUF_THLD_INT_ENA` writer - Receive Buffer threshold status enable."]
12pub type RX_DATA_BUF_THLD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `IBI_STATUS_THLD_INT_ENA` reader - Only used in master mode. IBI Buffer threshold status enable."]
14pub type IBI_STATUS_THLD_INT_ENA_R = crate::BitReader;
15#[doc = "Field `IBI_STATUS_THLD_INT_ENA` writer - Only used in master mode. IBI Buffer threshold status enable."]
16pub type IBI_STATUS_THLD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CMD_BUF_EMPTY_THLD_INT_ENA` reader - Command buffer ready status enable."]
18pub type CMD_BUF_EMPTY_THLD_INT_ENA_R = crate::BitReader;
19#[doc = "Field `CMD_BUF_EMPTY_THLD_INT_ENA` writer - Command buffer ready status enable."]
20pub type CMD_BUF_EMPTY_THLD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `RESP_READY_INT_ENA` reader - Response buffer ready status enable."]
22pub type RESP_READY_INT_ENA_R = crate::BitReader;
23#[doc = "Field `RESP_READY_INT_ENA` writer - Response buffer ready status enable."]
24pub type RESP_READY_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `NXT_CMD_REQ_ERR_INT_ENA` reader - next command request error status enable"]
26pub type NXT_CMD_REQ_ERR_INT_ENA_R = crate::BitReader;
27#[doc = "Field `NXT_CMD_REQ_ERR_INT_ENA` writer - next command request error status enable"]
28pub type NXT_CMD_REQ_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `TRANSFER_ERR_INT_ENA` reader - Transfer error status enable"]
30pub type TRANSFER_ERR_INT_ENA_R = crate::BitReader;
31#[doc = "Field `TRANSFER_ERR_INT_ENA` writer - Transfer error status enable"]
32pub type TRANSFER_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `TRANSFER_COMPLETE_INT_ENA` reader - NA"]
34pub type TRANSFER_COMPLETE_INT_ENA_R = crate::BitReader;
35#[doc = "Field `TRANSFER_COMPLETE_INT_ENA` writer - NA"]
36pub type TRANSFER_COMPLETE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `COMMAND_DONE_INT_ENA` reader - NA"]
38pub type COMMAND_DONE_INT_ENA_R = crate::BitReader;
39#[doc = "Field `COMMAND_DONE_INT_ENA` writer - NA"]
40pub type COMMAND_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `DETECT_START_INT_ENA` reader - NA"]
42pub type DETECT_START_INT_ENA_R = crate::BitReader;
43#[doc = "Field `DETECT_START_INT_ENA` writer - NA"]
44pub type DETECT_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `RESP_BUF_OVF_INT_ENA` reader - NA"]
46pub type RESP_BUF_OVF_INT_ENA_R = crate::BitReader;
47#[doc = "Field `RESP_BUF_OVF_INT_ENA` writer - NA"]
48pub type RESP_BUF_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `IBI_DATA_BUF_OVF_INT_ENA` reader - NA"]
50pub type IBI_DATA_BUF_OVF_INT_ENA_R = crate::BitReader;
51#[doc = "Field `IBI_DATA_BUF_OVF_INT_ENA` writer - NA"]
52pub type IBI_DATA_BUF_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `IBI_STATUS_BUF_OVF_INT_ENA` reader - NA"]
54pub type IBI_STATUS_BUF_OVF_INT_ENA_R = crate::BitReader;
55#[doc = "Field `IBI_STATUS_BUF_OVF_INT_ENA` writer - NA"]
56pub type IBI_STATUS_BUF_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `IBI_HANDLE_DONE_INT_ENA` reader - NA"]
58pub type IBI_HANDLE_DONE_INT_ENA_R = crate::BitReader;
59#[doc = "Field `IBI_HANDLE_DONE_INT_ENA` writer - NA"]
60pub type IBI_HANDLE_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `IBI_DETECT_INT_ENA` reader - NA"]
62pub type IBI_DETECT_INT_ENA_R = crate::BitReader;
63#[doc = "Field `IBI_DETECT_INT_ENA` writer - NA"]
64pub type IBI_DETECT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `CMD_CCC_MISMATCH_INT_ENA` reader - NA"]
66pub type CMD_CCC_MISMATCH_INT_ENA_R = crate::BitReader;
67#[doc = "Field `CMD_CCC_MISMATCH_INT_ENA` writer - NA"]
68pub type CMD_CCC_MISMATCH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
69impl R {
70 #[doc = "Bit 0 - Transmit Buffer threshold status enable."]
71 #[inline(always)]
72 pub fn tx_data_buf_thld_int_ena(&self) -> TX_DATA_BUF_THLD_INT_ENA_R {
73 TX_DATA_BUF_THLD_INT_ENA_R::new((self.bits & 1) != 0)
74 }
75 #[doc = "Bit 1 - Receive Buffer threshold status enable."]
76 #[inline(always)]
77 pub fn rx_data_buf_thld_int_ena(&self) -> RX_DATA_BUF_THLD_INT_ENA_R {
78 RX_DATA_BUF_THLD_INT_ENA_R::new(((self.bits >> 1) & 1) != 0)
79 }
80 #[doc = "Bit 2 - Only used in master mode. IBI Buffer threshold status enable."]
81 #[inline(always)]
82 pub fn ibi_status_thld_int_ena(&self) -> IBI_STATUS_THLD_INT_ENA_R {
83 IBI_STATUS_THLD_INT_ENA_R::new(((self.bits >> 2) & 1) != 0)
84 }
85 #[doc = "Bit 3 - Command buffer ready status enable."]
86 #[inline(always)]
87 pub fn cmd_buf_empty_thld_int_ena(&self) -> CMD_BUF_EMPTY_THLD_INT_ENA_R {
88 CMD_BUF_EMPTY_THLD_INT_ENA_R::new(((self.bits >> 3) & 1) != 0)
89 }
90 #[doc = "Bit 4 - Response buffer ready status enable."]
91 #[inline(always)]
92 pub fn resp_ready_int_ena(&self) -> RESP_READY_INT_ENA_R {
93 RESP_READY_INT_ENA_R::new(((self.bits >> 4) & 1) != 0)
94 }
95 #[doc = "Bit 5 - next command request error status enable"]
96 #[inline(always)]
97 pub fn nxt_cmd_req_err_int_ena(&self) -> NXT_CMD_REQ_ERR_INT_ENA_R {
98 NXT_CMD_REQ_ERR_INT_ENA_R::new(((self.bits >> 5) & 1) != 0)
99 }
100 #[doc = "Bit 6 - Transfer error status enable"]
101 #[inline(always)]
102 pub fn transfer_err_int_ena(&self) -> TRANSFER_ERR_INT_ENA_R {
103 TRANSFER_ERR_INT_ENA_R::new(((self.bits >> 6) & 1) != 0)
104 }
105 #[doc = "Bit 7 - NA"]
106 #[inline(always)]
107 pub fn transfer_complete_int_ena(&self) -> TRANSFER_COMPLETE_INT_ENA_R {
108 TRANSFER_COMPLETE_INT_ENA_R::new(((self.bits >> 7) & 1) != 0)
109 }
110 #[doc = "Bit 8 - NA"]
111 #[inline(always)]
112 pub fn command_done_int_ena(&self) -> COMMAND_DONE_INT_ENA_R {
113 COMMAND_DONE_INT_ENA_R::new(((self.bits >> 8) & 1) != 0)
114 }
115 #[doc = "Bit 9 - NA"]
116 #[inline(always)]
117 pub fn detect_start_int_ena(&self) -> DETECT_START_INT_ENA_R {
118 DETECT_START_INT_ENA_R::new(((self.bits >> 9) & 1) != 0)
119 }
120 #[doc = "Bit 10 - NA"]
121 #[inline(always)]
122 pub fn resp_buf_ovf_int_ena(&self) -> RESP_BUF_OVF_INT_ENA_R {
123 RESP_BUF_OVF_INT_ENA_R::new(((self.bits >> 10) & 1) != 0)
124 }
125 #[doc = "Bit 11 - NA"]
126 #[inline(always)]
127 pub fn ibi_data_buf_ovf_int_ena(&self) -> IBI_DATA_BUF_OVF_INT_ENA_R {
128 IBI_DATA_BUF_OVF_INT_ENA_R::new(((self.bits >> 11) & 1) != 0)
129 }
130 #[doc = "Bit 12 - NA"]
131 #[inline(always)]
132 pub fn ibi_status_buf_ovf_int_ena(&self) -> IBI_STATUS_BUF_OVF_INT_ENA_R {
133 IBI_STATUS_BUF_OVF_INT_ENA_R::new(((self.bits >> 12) & 1) != 0)
134 }
135 #[doc = "Bit 13 - NA"]
136 #[inline(always)]
137 pub fn ibi_handle_done_int_ena(&self) -> IBI_HANDLE_DONE_INT_ENA_R {
138 IBI_HANDLE_DONE_INT_ENA_R::new(((self.bits >> 13) & 1) != 0)
139 }
140 #[doc = "Bit 14 - NA"]
141 #[inline(always)]
142 pub fn ibi_detect_int_ena(&self) -> IBI_DETECT_INT_ENA_R {
143 IBI_DETECT_INT_ENA_R::new(((self.bits >> 14) & 1) != 0)
144 }
145 #[doc = "Bit 15 - NA"]
146 #[inline(always)]
147 pub fn cmd_ccc_mismatch_int_ena(&self) -> CMD_CCC_MISMATCH_INT_ENA_R {
148 CMD_CCC_MISMATCH_INT_ENA_R::new(((self.bits >> 15) & 1) != 0)
149 }
150}
151#[cfg(feature = "impl-register-debug")]
152impl core::fmt::Debug for R {
153 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
154 f.debug_struct("INT_ST_ENA")
155 .field(
156 "tx_data_buf_thld_int_ena",
157 &format_args!("{}", self.tx_data_buf_thld_int_ena().bit()),
158 )
159 .field(
160 "rx_data_buf_thld_int_ena",
161 &format_args!("{}", self.rx_data_buf_thld_int_ena().bit()),
162 )
163 .field(
164 "ibi_status_thld_int_ena",
165 &format_args!("{}", self.ibi_status_thld_int_ena().bit()),
166 )
167 .field(
168 "cmd_buf_empty_thld_int_ena",
169 &format_args!("{}", self.cmd_buf_empty_thld_int_ena().bit()),
170 )
171 .field(
172 "resp_ready_int_ena",
173 &format_args!("{}", self.resp_ready_int_ena().bit()),
174 )
175 .field(
176 "nxt_cmd_req_err_int_ena",
177 &format_args!("{}", self.nxt_cmd_req_err_int_ena().bit()),
178 )
179 .field(
180 "transfer_err_int_ena",
181 &format_args!("{}", self.transfer_err_int_ena().bit()),
182 )
183 .field(
184 "transfer_complete_int_ena",
185 &format_args!("{}", self.transfer_complete_int_ena().bit()),
186 )
187 .field(
188 "command_done_int_ena",
189 &format_args!("{}", self.command_done_int_ena().bit()),
190 )
191 .field(
192 "detect_start_int_ena",
193 &format_args!("{}", self.detect_start_int_ena().bit()),
194 )
195 .field(
196 "resp_buf_ovf_int_ena",
197 &format_args!("{}", self.resp_buf_ovf_int_ena().bit()),
198 )
199 .field(
200 "ibi_data_buf_ovf_int_ena",
201 &format_args!("{}", self.ibi_data_buf_ovf_int_ena().bit()),
202 )
203 .field(
204 "ibi_status_buf_ovf_int_ena",
205 &format_args!("{}", self.ibi_status_buf_ovf_int_ena().bit()),
206 )
207 .field(
208 "ibi_handle_done_int_ena",
209 &format_args!("{}", self.ibi_handle_done_int_ena().bit()),
210 )
211 .field(
212 "ibi_detect_int_ena",
213 &format_args!("{}", self.ibi_detect_int_ena().bit()),
214 )
215 .field(
216 "cmd_ccc_mismatch_int_ena",
217 &format_args!("{}", self.cmd_ccc_mismatch_int_ena().bit()),
218 )
219 .finish()
220 }
221}
222#[cfg(feature = "impl-register-debug")]
223impl core::fmt::Debug for crate::generic::Reg<INT_ST_ENA_SPEC> {
224 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
225 core::fmt::Debug::fmt(&self.read(), f)
226 }
227}
228impl W {
229 #[doc = "Bit 0 - Transmit Buffer threshold status enable."]
230 #[inline(always)]
231 #[must_use]
232 pub fn tx_data_buf_thld_int_ena(&mut self) -> TX_DATA_BUF_THLD_INT_ENA_W<INT_ST_ENA_SPEC> {
233 TX_DATA_BUF_THLD_INT_ENA_W::new(self, 0)
234 }
235 #[doc = "Bit 1 - Receive Buffer threshold status enable."]
236 #[inline(always)]
237 #[must_use]
238 pub fn rx_data_buf_thld_int_ena(&mut self) -> RX_DATA_BUF_THLD_INT_ENA_W<INT_ST_ENA_SPEC> {
239 RX_DATA_BUF_THLD_INT_ENA_W::new(self, 1)
240 }
241 #[doc = "Bit 2 - Only used in master mode. IBI Buffer threshold status enable."]
242 #[inline(always)]
243 #[must_use]
244 pub fn ibi_status_thld_int_ena(&mut self) -> IBI_STATUS_THLD_INT_ENA_W<INT_ST_ENA_SPEC> {
245 IBI_STATUS_THLD_INT_ENA_W::new(self, 2)
246 }
247 #[doc = "Bit 3 - Command buffer ready status enable."]
248 #[inline(always)]
249 #[must_use]
250 pub fn cmd_buf_empty_thld_int_ena(&mut self) -> CMD_BUF_EMPTY_THLD_INT_ENA_W<INT_ST_ENA_SPEC> {
251 CMD_BUF_EMPTY_THLD_INT_ENA_W::new(self, 3)
252 }
253 #[doc = "Bit 4 - Response buffer ready status enable."]
254 #[inline(always)]
255 #[must_use]
256 pub fn resp_ready_int_ena(&mut self) -> RESP_READY_INT_ENA_W<INT_ST_ENA_SPEC> {
257 RESP_READY_INT_ENA_W::new(self, 4)
258 }
259 #[doc = "Bit 5 - next command request error status enable"]
260 #[inline(always)]
261 #[must_use]
262 pub fn nxt_cmd_req_err_int_ena(&mut self) -> NXT_CMD_REQ_ERR_INT_ENA_W<INT_ST_ENA_SPEC> {
263 NXT_CMD_REQ_ERR_INT_ENA_W::new(self, 5)
264 }
265 #[doc = "Bit 6 - Transfer error status enable"]
266 #[inline(always)]
267 #[must_use]
268 pub fn transfer_err_int_ena(&mut self) -> TRANSFER_ERR_INT_ENA_W<INT_ST_ENA_SPEC> {
269 TRANSFER_ERR_INT_ENA_W::new(self, 6)
270 }
271 #[doc = "Bit 7 - NA"]
272 #[inline(always)]
273 #[must_use]
274 pub fn transfer_complete_int_ena(&mut self) -> TRANSFER_COMPLETE_INT_ENA_W<INT_ST_ENA_SPEC> {
275 TRANSFER_COMPLETE_INT_ENA_W::new(self, 7)
276 }
277 #[doc = "Bit 8 - NA"]
278 #[inline(always)]
279 #[must_use]
280 pub fn command_done_int_ena(&mut self) -> COMMAND_DONE_INT_ENA_W<INT_ST_ENA_SPEC> {
281 COMMAND_DONE_INT_ENA_W::new(self, 8)
282 }
283 #[doc = "Bit 9 - NA"]
284 #[inline(always)]
285 #[must_use]
286 pub fn detect_start_int_ena(&mut self) -> DETECT_START_INT_ENA_W<INT_ST_ENA_SPEC> {
287 DETECT_START_INT_ENA_W::new(self, 9)
288 }
289 #[doc = "Bit 10 - NA"]
290 #[inline(always)]
291 #[must_use]
292 pub fn resp_buf_ovf_int_ena(&mut self) -> RESP_BUF_OVF_INT_ENA_W<INT_ST_ENA_SPEC> {
293 RESP_BUF_OVF_INT_ENA_W::new(self, 10)
294 }
295 #[doc = "Bit 11 - NA"]
296 #[inline(always)]
297 #[must_use]
298 pub fn ibi_data_buf_ovf_int_ena(&mut self) -> IBI_DATA_BUF_OVF_INT_ENA_W<INT_ST_ENA_SPEC> {
299 IBI_DATA_BUF_OVF_INT_ENA_W::new(self, 11)
300 }
301 #[doc = "Bit 12 - NA"]
302 #[inline(always)]
303 #[must_use]
304 pub fn ibi_status_buf_ovf_int_ena(&mut self) -> IBI_STATUS_BUF_OVF_INT_ENA_W<INT_ST_ENA_SPEC> {
305 IBI_STATUS_BUF_OVF_INT_ENA_W::new(self, 12)
306 }
307 #[doc = "Bit 13 - NA"]
308 #[inline(always)]
309 #[must_use]
310 pub fn ibi_handle_done_int_ena(&mut self) -> IBI_HANDLE_DONE_INT_ENA_W<INT_ST_ENA_SPEC> {
311 IBI_HANDLE_DONE_INT_ENA_W::new(self, 13)
312 }
313 #[doc = "Bit 14 - NA"]
314 #[inline(always)]
315 #[must_use]
316 pub fn ibi_detect_int_ena(&mut self) -> IBI_DETECT_INT_ENA_W<INT_ST_ENA_SPEC> {
317 IBI_DETECT_INT_ENA_W::new(self, 14)
318 }
319 #[doc = "Bit 15 - NA"]
320 #[inline(always)]
321 #[must_use]
322 pub fn cmd_ccc_mismatch_int_ena(&mut self) -> CMD_CCC_MISMATCH_INT_ENA_W<INT_ST_ENA_SPEC> {
323 CMD_CCC_MISMATCH_INT_ENA_W::new(self, 15)
324 }
325}
326#[doc = "The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_st_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
327pub struct INT_ST_ENA_SPEC;
328impl crate::RegisterSpec for INT_ST_ENA_SPEC {
329 type Ux = u32;
330}
331#[doc = "`read()` method returns [`int_st_ena::R`](R) reader structure"]
332impl crate::Readable for INT_ST_ENA_SPEC {}
333#[doc = "`write(|w| ..)` method takes [`int_st_ena::W`](W) writer structure"]
334impl crate::Writable for INT_ST_ENA_SPEC {
335 type Safety = crate::Unsafe;
336 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
337 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
338}
339#[doc = "`reset()` method sets INT_ST_ENA to value 0"]
340impl crate::Resettable for INT_ST_ENA_SPEC {
341 const RESET_VALUE: u32 = 0;
342}