esp32p4/i3c_mst/
int_st.rs1#[doc = "Register `INT_ST` reader"]
2pub type R = crate::R<INT_ST_SPEC>;
3#[doc = "Field `TX_DATA_BUF_THLD_INT_ST` reader - This interrupt is generated when number of empty locations in transmit buffer is greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in transmit buffer is less than threshold value."]
4pub type TX_DATA_BUF_THLD_INT_ST_R = crate::BitReader;
5#[doc = "Field `RX_DATA_BUF_THLD_INT_ST` reader - This interrupt is generated when number of entries in receive buffer is greater than or equal to threshold value specified by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in receive buffer is less than threshold value."]
6pub type RX_DATA_BUF_THLD_INT_ST_R = crate::BitReader;
7#[doc = "Field `IBI_STATUS_THLD_INT_ST` reader - Only used in master mode. This interrupt is generated when number of entries in IBI buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in IBI buffer is less than threshold value."]
8pub type IBI_STATUS_THLD_INT_ST_R = crate::BitReader;
9#[doc = "Field `CMD_BUF_EMPTY_THLD_INT_ST` reader - This interrupt is generated when number of empty locations in command buffer is greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in command buffer is less than threshold value."]
10pub type CMD_BUF_EMPTY_THLD_INT_ST_R = crate::BitReader;
11#[doc = "Field `RESP_READY_INT_ST` reader - This interrupt is generated when number of entries in response buffer is greater than or equal to threshold value specified by RESP_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in response buffer is less than threshold value."]
12pub type RESP_READY_INT_ST_R = crate::BitReader;
13#[doc = "Field `NXT_CMD_REQ_ERR_INT_ST` reader - This interrupt is generated if toc is 0(master will restart next command), but command buf is empty."]
14pub type NXT_CMD_REQ_ERR_INT_ST_R = crate::BitReader;
15#[doc = "Field `TRANSFER_ERR_INT_ST` reader - This interrupt is generated if any error occurs during transfer. The error type will be specified in the response packet associated with the command (in ERR_STATUS field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1."]
16pub type TRANSFER_ERR_INT_ST_R = crate::BitReader;
17#[doc = "Field `TRANSFER_COMPLETE_INT_ST` reader - NA"]
18pub type TRANSFER_COMPLETE_INT_ST_R = crate::BitReader;
19#[doc = "Field `COMMAND_DONE_INT_ST` reader - NA"]
20pub type COMMAND_DONE_INT_ST_R = crate::BitReader;
21#[doc = "Field `DETECT_START_INT_ST` reader - NA"]
22pub type DETECT_START_INT_ST_R = crate::BitReader;
23#[doc = "Field `RESP_BUF_OVF_INT_ST` reader - NA"]
24pub type RESP_BUF_OVF_INT_ST_R = crate::BitReader;
25#[doc = "Field `IBI_DATA_BUF_OVF_INT_ST` reader - NA"]
26pub type IBI_DATA_BUF_OVF_INT_ST_R = crate::BitReader;
27#[doc = "Field `IBI_STATUS_BUF_OVF_INT_ST` reader - NA"]
28pub type IBI_STATUS_BUF_OVF_INT_ST_R = crate::BitReader;
29#[doc = "Field `IBI_HANDLE_DONE_INT_ST` reader - NA"]
30pub type IBI_HANDLE_DONE_INT_ST_R = crate::BitReader;
31#[doc = "Field `IBI_DETECT_INT_ST` reader - NA"]
32pub type IBI_DETECT_INT_ST_R = crate::BitReader;
33#[doc = "Field `CMD_CCC_MISMATCH_INT_ST` reader - NA"]
34pub type CMD_CCC_MISMATCH_INT_ST_R = crate::BitReader;
35impl R {
36 #[doc = "Bit 0 - This interrupt is generated when number of empty locations in transmit buffer is greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in transmit buffer is less than threshold value."]
37 #[inline(always)]
38 pub fn tx_data_buf_thld_int_st(&self) -> TX_DATA_BUF_THLD_INT_ST_R {
39 TX_DATA_BUF_THLD_INT_ST_R::new((self.bits & 1) != 0)
40 }
41 #[doc = "Bit 1 - This interrupt is generated when number of entries in receive buffer is greater than or equal to threshold value specified by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in receive buffer is less than threshold value."]
42 #[inline(always)]
43 pub fn rx_data_buf_thld_int_st(&self) -> RX_DATA_BUF_THLD_INT_ST_R {
44 RX_DATA_BUF_THLD_INT_ST_R::new(((self.bits >> 1) & 1) != 0)
45 }
46 #[doc = "Bit 2 - Only used in master mode. This interrupt is generated when number of entries in IBI buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in IBI buffer is less than threshold value."]
47 #[inline(always)]
48 pub fn ibi_status_thld_int_st(&self) -> IBI_STATUS_THLD_INT_ST_R {
49 IBI_STATUS_THLD_INT_ST_R::new(((self.bits >> 2) & 1) != 0)
50 }
51 #[doc = "Bit 3 - This interrupt is generated when number of empty locations in command buffer is greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in command buffer is less than threshold value."]
52 #[inline(always)]
53 pub fn cmd_buf_empty_thld_int_st(&self) -> CMD_BUF_EMPTY_THLD_INT_ST_R {
54 CMD_BUF_EMPTY_THLD_INT_ST_R::new(((self.bits >> 3) & 1) != 0)
55 }
56 #[doc = "Bit 4 - This interrupt is generated when number of entries in response buffer is greater than or equal to threshold value specified by RESP_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in response buffer is less than threshold value."]
57 #[inline(always)]
58 pub fn resp_ready_int_st(&self) -> RESP_READY_INT_ST_R {
59 RESP_READY_INT_ST_R::new(((self.bits >> 4) & 1) != 0)
60 }
61 #[doc = "Bit 5 - This interrupt is generated if toc is 0(master will restart next command), but command buf is empty."]
62 #[inline(always)]
63 pub fn nxt_cmd_req_err_int_st(&self) -> NXT_CMD_REQ_ERR_INT_ST_R {
64 NXT_CMD_REQ_ERR_INT_ST_R::new(((self.bits >> 5) & 1) != 0)
65 }
66 #[doc = "Bit 6 - This interrupt is generated if any error occurs during transfer. The error type will be specified in the response packet associated with the command (in ERR_STATUS field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1."]
67 #[inline(always)]
68 pub fn transfer_err_int_st(&self) -> TRANSFER_ERR_INT_ST_R {
69 TRANSFER_ERR_INT_ST_R::new(((self.bits >> 6) & 1) != 0)
70 }
71 #[doc = "Bit 7 - NA"]
72 #[inline(always)]
73 pub fn transfer_complete_int_st(&self) -> TRANSFER_COMPLETE_INT_ST_R {
74 TRANSFER_COMPLETE_INT_ST_R::new(((self.bits >> 7) & 1) != 0)
75 }
76 #[doc = "Bit 8 - NA"]
77 #[inline(always)]
78 pub fn command_done_int_st(&self) -> COMMAND_DONE_INT_ST_R {
79 COMMAND_DONE_INT_ST_R::new(((self.bits >> 8) & 1) != 0)
80 }
81 #[doc = "Bit 9 - NA"]
82 #[inline(always)]
83 pub fn detect_start_int_st(&self) -> DETECT_START_INT_ST_R {
84 DETECT_START_INT_ST_R::new(((self.bits >> 9) & 1) != 0)
85 }
86 #[doc = "Bit 10 - NA"]
87 #[inline(always)]
88 pub fn resp_buf_ovf_int_st(&self) -> RESP_BUF_OVF_INT_ST_R {
89 RESP_BUF_OVF_INT_ST_R::new(((self.bits >> 10) & 1) != 0)
90 }
91 #[doc = "Bit 11 - NA"]
92 #[inline(always)]
93 pub fn ibi_data_buf_ovf_int_st(&self) -> IBI_DATA_BUF_OVF_INT_ST_R {
94 IBI_DATA_BUF_OVF_INT_ST_R::new(((self.bits >> 11) & 1) != 0)
95 }
96 #[doc = "Bit 12 - NA"]
97 #[inline(always)]
98 pub fn ibi_status_buf_ovf_int_st(&self) -> IBI_STATUS_BUF_OVF_INT_ST_R {
99 IBI_STATUS_BUF_OVF_INT_ST_R::new(((self.bits >> 12) & 1) != 0)
100 }
101 #[doc = "Bit 13 - NA"]
102 #[inline(always)]
103 pub fn ibi_handle_done_int_st(&self) -> IBI_HANDLE_DONE_INT_ST_R {
104 IBI_HANDLE_DONE_INT_ST_R::new(((self.bits >> 13) & 1) != 0)
105 }
106 #[doc = "Bit 14 - NA"]
107 #[inline(always)]
108 pub fn ibi_detect_int_st(&self) -> IBI_DETECT_INT_ST_R {
109 IBI_DETECT_INT_ST_R::new(((self.bits >> 14) & 1) != 0)
110 }
111 #[doc = "Bit 15 - NA"]
112 #[inline(always)]
113 pub fn cmd_ccc_mismatch_int_st(&self) -> CMD_CCC_MISMATCH_INT_ST_R {
114 CMD_CCC_MISMATCH_INT_ST_R::new(((self.bits >> 15) & 1) != 0)
115 }
116}
117#[cfg(feature = "impl-register-debug")]
118impl core::fmt::Debug for R {
119 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
120 f.debug_struct("INT_ST")
121 .field(
122 "tx_data_buf_thld_int_st",
123 &format_args!("{}", self.tx_data_buf_thld_int_st().bit()),
124 )
125 .field(
126 "rx_data_buf_thld_int_st",
127 &format_args!("{}", self.rx_data_buf_thld_int_st().bit()),
128 )
129 .field(
130 "ibi_status_thld_int_st",
131 &format_args!("{}", self.ibi_status_thld_int_st().bit()),
132 )
133 .field(
134 "cmd_buf_empty_thld_int_st",
135 &format_args!("{}", self.cmd_buf_empty_thld_int_st().bit()),
136 )
137 .field(
138 "resp_ready_int_st",
139 &format_args!("{}", self.resp_ready_int_st().bit()),
140 )
141 .field(
142 "nxt_cmd_req_err_int_st",
143 &format_args!("{}", self.nxt_cmd_req_err_int_st().bit()),
144 )
145 .field(
146 "transfer_err_int_st",
147 &format_args!("{}", self.transfer_err_int_st().bit()),
148 )
149 .field(
150 "transfer_complete_int_st",
151 &format_args!("{}", self.transfer_complete_int_st().bit()),
152 )
153 .field(
154 "command_done_int_st",
155 &format_args!("{}", self.command_done_int_st().bit()),
156 )
157 .field(
158 "detect_start_int_st",
159 &format_args!("{}", self.detect_start_int_st().bit()),
160 )
161 .field(
162 "resp_buf_ovf_int_st",
163 &format_args!("{}", self.resp_buf_ovf_int_st().bit()),
164 )
165 .field(
166 "ibi_data_buf_ovf_int_st",
167 &format_args!("{}", self.ibi_data_buf_ovf_int_st().bit()),
168 )
169 .field(
170 "ibi_status_buf_ovf_int_st",
171 &format_args!("{}", self.ibi_status_buf_ovf_int_st().bit()),
172 )
173 .field(
174 "ibi_handle_done_int_st",
175 &format_args!("{}", self.ibi_handle_done_int_st().bit()),
176 )
177 .field(
178 "ibi_detect_int_st",
179 &format_args!("{}", self.ibi_detect_int_st().bit()),
180 )
181 .field(
182 "cmd_ccc_mismatch_int_st",
183 &format_args!("{}", self.cmd_ccc_mismatch_int_st().bit()),
184 )
185 .finish()
186 }
187}
188#[cfg(feature = "impl-register-debug")]
189impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
190 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
191 core::fmt::Debug::fmt(&self.read(), f)
192 }
193}
194#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
195pub struct INT_ST_SPEC;
196impl crate::RegisterSpec for INT_ST_SPEC {
197 type Ux = u32;
198}
199#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
200impl crate::Readable for INT_ST_SPEC {}
201#[doc = "`reset()` method sets INT_ST to value 0"]
202impl crate::Resettable for INT_ST_SPEC {
203 const RESET_VALUE: u32 = 0;
204}