esp32p4/i3c_mst/
bus_free_time.rs

1#[doc = "Register `BUS_FREE_TIME` reader"]
2pub type R = crate::R<BUS_FREE_TIME_SPEC>;
3#[doc = "Register `BUS_FREE_TIME` writer"]
4pub type W = crate::W<BUS_FREE_TIME_SPEC>;
5#[doc = "Field `REG_BUS_FREE_TIME` reader - I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus System, this field represents tCAS. In Mixed Bus System, this field is expected to be programmed to tLOW of I2C Timing."]
6pub type REG_BUS_FREE_TIME_R = crate::FieldReader<u16>;
7#[doc = "Field `REG_BUS_FREE_TIME` writer - I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus System, this field represents tCAS. In Mixed Bus System, this field is expected to be programmed to tLOW of I2C Timing."]
8pub type REG_BUS_FREE_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9impl R {
10    #[doc = "Bits 0:15 - I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus System, this field represents tCAS. In Mixed Bus System, this field is expected to be programmed to tLOW of I2C Timing."]
11    #[inline(always)]
12    pub fn reg_bus_free_time(&self) -> REG_BUS_FREE_TIME_R {
13        REG_BUS_FREE_TIME_R::new((self.bits & 0xffff) as u16)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("BUS_FREE_TIME")
20            .field(
21                "reg_bus_free_time",
22                &format_args!("{}", self.reg_bus_free_time().bits()),
23            )
24            .finish()
25    }
26}
27#[cfg(feature = "impl-register-debug")]
28impl core::fmt::Debug for crate::generic::Reg<BUS_FREE_TIME_SPEC> {
29    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
30        core::fmt::Debug::fmt(&self.read(), f)
31    }
32}
33impl W {
34    #[doc = "Bits 0:15 - I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus System, this field represents tCAS. In Mixed Bus System, this field is expected to be programmed to tLOW of I2C Timing."]
35    #[inline(always)]
36    #[must_use]
37    pub fn reg_bus_free_time(&mut self) -> REG_BUS_FREE_TIME_W<BUS_FREE_TIME_SPEC> {
38        REG_BUS_FREE_TIME_W::new(self, 0)
39    }
40}
41#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_free_time::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bus_free_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
42pub struct BUS_FREE_TIME_SPEC;
43impl crate::RegisterSpec for BUS_FREE_TIME_SPEC {
44    type Ux = u32;
45}
46#[doc = "`read()` method returns [`bus_free_time::R`](R) reader structure"]
47impl crate::Readable for BUS_FREE_TIME_SPEC {}
48#[doc = "`write(|w| ..)` method takes [`bus_free_time::W`](W) writer structure"]
49impl crate::Writable for BUS_FREE_TIME_SPEC {
50    type Safety = crate::Unsafe;
51    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
52    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
53}
54#[doc = "`reset()` method sets BUS_FREE_TIME to value 0x05"]
55impl crate::Resettable for BUS_FREE_TIME_SPEC {
56    const RESET_VALUE: u32 = 0x05;
57}
esp32p4/i3c_mst/bus_free_time.rs

esp32p4/i3c_mst/
bus_free_time.rs
