1#[doc = "Register `CTR` reader"]
2pub type R = crate::R<CTR_SPEC>;
3#[doc = "Register `CTR` writer"]
4pub type W = crate::W<CTR_SPEC>;
5#[doc = "Field `SDA_FORCE_OUT` reader - Configures the SDA output mode 1: Direct output, 0: Open drain output."]
6pub type SDA_FORCE_OUT_R = crate::BitReader;
7#[doc = "Field `SDA_FORCE_OUT` writer - Configures the SDA output mode 1: Direct output, 0: Open drain output."]
8pub type SDA_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SCL_FORCE_OUT` reader - Configures the SCL output mode 1: Direct output, 0: Open drain output."]
10pub type SCL_FORCE_OUT_R = crate::BitReader;
11#[doc = "Field `SCL_FORCE_OUT` writer - Configures the SCL output mode 1: Direct output, 0: Open drain output."]
12pub type SCL_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SAMPLE_SCL_LEVEL` reader - Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level. 0: Sample SDA data on the SCL high level."]
14pub type SAMPLE_SCL_LEVEL_R = crate::BitReader;
15#[doc = "Field `SAMPLE_SCL_LEVEL` writer - Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level. 0: Sample SDA data on the SCL high level."]
16pub type SAMPLE_SCL_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RX_FULL_ACK_LEVEL` reader - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold."]
18pub type RX_FULL_ACK_LEVEL_R = crate::BitReader;
19#[doc = "Field `RX_FULL_ACK_LEVEL` writer - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold."]
20pub type RX_FULL_ACK_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `MS_MODE` reader - Configures the module as an I2C Master or Slave. 0: Slave 1: Master"]
22pub type MS_MODE_R = crate::BitReader;
23#[doc = "Field `MS_MODE` writer - Configures the module as an I2C Master or Slave. 0: Slave 1: Master"]
24pub type MS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `TRANS_START` writer - Configures to start sending the data in txfifo for slave. 0: No effect 1: Start"]
26pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `TX_LSB_FIRST` reader - Configures to control the sending order for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."]
28pub type TX_LSB_FIRST_R = crate::BitReader;
29#[doc = "Field `TX_LSB_FIRST` writer - Configures to control the sending order for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."]
30pub type TX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `RX_LSB_FIRST` reader - Configures to control the storage order for received data. 1: receive data from the least significant bit 0: receive data from the most significant bit."]
32pub type RX_LSB_FIRST_R = crate::BitReader;
33#[doc = "Field `RX_LSB_FIRST` writer - Configures to control the storage order for received data. 1: receive data from the least significant bit 0: receive data from the most significant bit."]
34pub type RX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `CLK_EN` reader - Configures whether to gate clock signal for registers. 0: Force clock on for registers 1: Support clock only when registers are read or written to by software."]
36pub type CLK_EN_R = crate::BitReader;
37#[doc = "Field `CLK_EN` writer - Configures whether to gate clock signal for registers. 0: Force clock on for registers 1: Support clock only when registers are read or written to by software."]
38pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `ARBITRATION_EN` reader - Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable"]
40pub type ARBITRATION_EN_R = crate::BitReader;
41#[doc = "Field `ARBITRATION_EN` writer - Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable"]
42pub type ARBITRATION_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
43#[doc = "Field `FSM_RST` writer - Configures to reset the SCL_FSM. 0: No effect 1: Reset"]
44pub type FSM_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `CONF_UPGATE` writer - Configures this bit for synchronization 0: No effect 1: Synchronize"]
46pub type CONF_UPGATE_W<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `SLV_TX_AUTO_START_EN` reader - Configures to enable slave to send data automatically 0: Disable 1: Enable"]
48pub type SLV_TX_AUTO_START_EN_R = crate::BitReader;
49#[doc = "Field `SLV_TX_AUTO_START_EN` writer - Configures to enable slave to send data automatically 0: Disable 1: Enable"]
50pub type SLV_TX_AUTO_START_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
51#[doc = "Field `ADDR_10BIT_RW_CHECK_EN` reader - Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. 0: Not check 1: Check"]
52pub type ADDR_10BIT_RW_CHECK_EN_R = crate::BitReader;
53#[doc = "Field `ADDR_10BIT_RW_CHECK_EN` writer - Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. 0: Not check 1: Check"]
54pub type ADDR_10BIT_RW_CHECK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
55#[doc = "Field `ADDR_BROADCASTING_EN` reader - Configures to support the 7bit general call function. 0: Not support 1: Support"]
56pub type ADDR_BROADCASTING_EN_R = crate::BitReader;
57#[doc = "Field `ADDR_BROADCASTING_EN` writer - Configures to support the 7bit general call function. 0: Not support 1: Support"]
58pub type ADDR_BROADCASTING_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
59impl R {
60 #[doc = "Bit 0 - Configures the SDA output mode 1: Direct output, 0: Open drain output."]
61 #[inline(always)]
62 pub fn sda_force_out(&self) -> SDA_FORCE_OUT_R {
63 SDA_FORCE_OUT_R::new((self.bits & 1) != 0)
64 }
65 #[doc = "Bit 1 - Configures the SCL output mode 1: Direct output, 0: Open drain output."]
66 #[inline(always)]
67 pub fn scl_force_out(&self) -> SCL_FORCE_OUT_R {
68 SCL_FORCE_OUT_R::new(((self.bits >> 1) & 1) != 0)
69 }
70 #[doc = "Bit 2 - Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level. 0: Sample SDA data on the SCL high level."]
71 #[inline(always)]
72 pub fn sample_scl_level(&self) -> SAMPLE_SCL_LEVEL_R {
73 SAMPLE_SCL_LEVEL_R::new(((self.bits >> 2) & 1) != 0)
74 }
75 #[doc = "Bit 3 - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold."]
76 #[inline(always)]
77 pub fn rx_full_ack_level(&self) -> RX_FULL_ACK_LEVEL_R {
78 RX_FULL_ACK_LEVEL_R::new(((self.bits >> 3) & 1) != 0)
79 }
80 #[doc = "Bit 4 - Configures the module as an I2C Master or Slave. 0: Slave 1: Master"]
81 #[inline(always)]
82 pub fn ms_mode(&self) -> MS_MODE_R {
83 MS_MODE_R::new(((self.bits >> 4) & 1) != 0)
84 }
85 #[doc = "Bit 6 - Configures to control the sending order for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."]
86 #[inline(always)]
87 pub fn tx_lsb_first(&self) -> TX_LSB_FIRST_R {
88 TX_LSB_FIRST_R::new(((self.bits >> 6) & 1) != 0)
89 }
90 #[doc = "Bit 7 - Configures to control the storage order for received data. 1: receive data from the least significant bit 0: receive data from the most significant bit."]
91 #[inline(always)]
92 pub fn rx_lsb_first(&self) -> RX_LSB_FIRST_R {
93 RX_LSB_FIRST_R::new(((self.bits >> 7) & 1) != 0)
94 }
95 #[doc = "Bit 8 - Configures whether to gate clock signal for registers. 0: Force clock on for registers 1: Support clock only when registers are read or written to by software."]
96 #[inline(always)]
97 pub fn clk_en(&self) -> CLK_EN_R {
98 CLK_EN_R::new(((self.bits >> 8) & 1) != 0)
99 }
100 #[doc = "Bit 9 - Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable"]
101 #[inline(always)]
102 pub fn arbitration_en(&self) -> ARBITRATION_EN_R {
103 ARBITRATION_EN_R::new(((self.bits >> 9) & 1) != 0)
104 }
105 #[doc = "Bit 12 - Configures to enable slave to send data automatically 0: Disable 1: Enable"]
106 #[inline(always)]
107 pub fn slv_tx_auto_start_en(&self) -> SLV_TX_AUTO_START_EN_R {
108 SLV_TX_AUTO_START_EN_R::new(((self.bits >> 12) & 1) != 0)
109 }
110 #[doc = "Bit 13 - Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. 0: Not check 1: Check"]
111 #[inline(always)]
112 pub fn addr_10bit_rw_check_en(&self) -> ADDR_10BIT_RW_CHECK_EN_R {
113 ADDR_10BIT_RW_CHECK_EN_R::new(((self.bits >> 13) & 1) != 0)
114 }
115 #[doc = "Bit 14 - Configures to support the 7bit general call function. 0: Not support 1: Support"]
116 #[inline(always)]
117 pub fn addr_broadcasting_en(&self) -> ADDR_BROADCASTING_EN_R {
118 ADDR_BROADCASTING_EN_R::new(((self.bits >> 14) & 1) != 0)
119 }
120}
121#[cfg(feature = "impl-register-debug")]
122impl core::fmt::Debug for R {
123 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
124 f.debug_struct("CTR")
125 .field(
126 "sda_force_out",
127 &format_args!("{}", self.sda_force_out().bit()),
128 )
129 .field(
130 "scl_force_out",
131 &format_args!("{}", self.scl_force_out().bit()),
132 )
133 .field(
134 "sample_scl_level",
135 &format_args!("{}", self.sample_scl_level().bit()),
136 )
137 .field(
138 "rx_full_ack_level",
139 &format_args!("{}", self.rx_full_ack_level().bit()),
140 )
141 .field("ms_mode", &format_args!("{}", self.ms_mode().bit()))
142 .field(
143 "tx_lsb_first",
144 &format_args!("{}", self.tx_lsb_first().bit()),
145 )
146 .field(
147 "rx_lsb_first",
148 &format_args!("{}", self.rx_lsb_first().bit()),
149 )
150 .field("clk_en", &format_args!("{}", self.clk_en().bit()))
151 .field(
152 "arbitration_en",
153 &format_args!("{}", self.arbitration_en().bit()),
154 )
155 .field(
156 "slv_tx_auto_start_en",
157 &format_args!("{}", self.slv_tx_auto_start_en().bit()),
158 )
159 .field(
160 "addr_10bit_rw_check_en",
161 &format_args!("{}", self.addr_10bit_rw_check_en().bit()),
162 )
163 .field(
164 "addr_broadcasting_en",
165 &format_args!("{}", self.addr_broadcasting_en().bit()),
166 )
167 .finish()
168 }
169}
170#[cfg(feature = "impl-register-debug")]
171impl core::fmt::Debug for crate::generic::Reg<CTR_SPEC> {
172 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
173 core::fmt::Debug::fmt(&self.read(), f)
174 }
175}
176impl W {
177 #[doc = "Bit 0 - Configures the SDA output mode 1: Direct output, 0: Open drain output."]
178 #[inline(always)]
179 #[must_use]
180 pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<CTR_SPEC> {
181 SDA_FORCE_OUT_W::new(self, 0)
182 }
183 #[doc = "Bit 1 - Configures the SCL output mode 1: Direct output, 0: Open drain output."]
184 #[inline(always)]
185 #[must_use]
186 pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<CTR_SPEC> {
187 SCL_FORCE_OUT_W::new(self, 1)
188 }
189 #[doc = "Bit 2 - Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level. 0: Sample SDA data on the SCL high level."]
190 #[inline(always)]
191 #[must_use]
192 pub fn sample_scl_level(&mut self) -> SAMPLE_SCL_LEVEL_W<CTR_SPEC> {
193 SAMPLE_SCL_LEVEL_W::new(self, 2)
194 }
195 #[doc = "Bit 3 - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold."]
196 #[inline(always)]
197 #[must_use]
198 pub fn rx_full_ack_level(&mut self) -> RX_FULL_ACK_LEVEL_W<CTR_SPEC> {
199 RX_FULL_ACK_LEVEL_W::new(self, 3)
200 }
201 #[doc = "Bit 4 - Configures the module as an I2C Master or Slave. 0: Slave 1: Master"]
202 #[inline(always)]
203 #[must_use]
204 pub fn ms_mode(&mut self) -> MS_MODE_W<CTR_SPEC> {
205 MS_MODE_W::new(self, 4)
206 }
207 #[doc = "Bit 5 - Configures to start sending the data in txfifo for slave. 0: No effect 1: Start"]
208 #[inline(always)]
209 #[must_use]
210 pub fn trans_start(&mut self) -> TRANS_START_W<CTR_SPEC> {
211 TRANS_START_W::new(self, 5)
212 }
213 #[doc = "Bit 6 - Configures to control the sending order for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."]
214 #[inline(always)]
215 #[must_use]
216 pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<CTR_SPEC> {
217 TX_LSB_FIRST_W::new(self, 6)
218 }
219 #[doc = "Bit 7 - Configures to control the storage order for received data. 1: receive data from the least significant bit 0: receive data from the most significant bit."]
220 #[inline(always)]
221 #[must_use]
222 pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<CTR_SPEC> {
223 RX_LSB_FIRST_W::new(self, 7)
224 }
225 #[doc = "Bit 8 - Configures whether to gate clock signal for registers. 0: Force clock on for registers 1: Support clock only when registers are read or written to by software."]
226 #[inline(always)]
227 #[must_use]
228 pub fn clk_en(&mut self) -> CLK_EN_W<CTR_SPEC> {
229 CLK_EN_W::new(self, 8)
230 }
231 #[doc = "Bit 9 - Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable"]
232 #[inline(always)]
233 #[must_use]
234 pub fn arbitration_en(&mut self) -> ARBITRATION_EN_W<CTR_SPEC> {
235 ARBITRATION_EN_W::new(self, 9)
236 }
237 #[doc = "Bit 10 - Configures to reset the SCL_FSM. 0: No effect 1: Reset"]
238 #[inline(always)]
239 #[must_use]
240 pub fn fsm_rst(&mut self) -> FSM_RST_W<CTR_SPEC> {
241 FSM_RST_W::new(self, 10)
242 }
243 #[doc = "Bit 11 - Configures this bit for synchronization 0: No effect 1: Synchronize"]
244 #[inline(always)]
245 #[must_use]
246 pub fn conf_upgate(&mut self) -> CONF_UPGATE_W<CTR_SPEC> {
247 CONF_UPGATE_W::new(self, 11)
248 }
249 #[doc = "Bit 12 - Configures to enable slave to send data automatically 0: Disable 1: Enable"]
250 #[inline(always)]
251 #[must_use]
252 pub fn slv_tx_auto_start_en(&mut self) -> SLV_TX_AUTO_START_EN_W<CTR_SPEC> {
253 SLV_TX_AUTO_START_EN_W::new(self, 12)
254 }
255 #[doc = "Bit 13 - Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. 0: Not check 1: Check"]
256 #[inline(always)]
257 #[must_use]
258 pub fn addr_10bit_rw_check_en(&mut self) -> ADDR_10BIT_RW_CHECK_EN_W<CTR_SPEC> {
259 ADDR_10BIT_RW_CHECK_EN_W::new(self, 13)
260 }
261 #[doc = "Bit 14 - Configures to support the 7bit general call function. 0: Not support 1: Support"]
262 #[inline(always)]
263 #[must_use]
264 pub fn addr_broadcasting_en(&mut self) -> ADDR_BROADCASTING_EN_W<CTR_SPEC> {
265 ADDR_BROADCASTING_EN_W::new(self, 14)
266 }
267}
268#[doc = "Transmission setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
269pub struct CTR_SPEC;
270impl crate::RegisterSpec for CTR_SPEC {
271 type Ux = u32;
272}
273#[doc = "`read()` method returns [`ctr::R`](R) reader structure"]
274impl crate::Readable for CTR_SPEC {}
275#[doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"]
276impl crate::Writable for CTR_SPEC {
277 type Safety = crate::Unsafe;
278 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
279 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
280}
281#[doc = "`reset()` method sets CTR to value 0x0208"]
282impl crate::Resettable for CTR_SPEC {
283 const RESET_VALUE: u32 = 0x0208;
284}