esp32p4/hp_sys_clkrst/
peri_clk_ctrl24.rs

1#[doc = "Register `PERI_CLK_CTRL24` reader"]
2pub type R = crate::R<PERI_CLK_CTRL24_SPEC>;
3#[doc = "Register `PERI_CLK_CTRL24` writer"]
4pub type W = crate::W<PERI_CLK_CTRL24_SPEC>;
5#[doc = "Field `ADC_SAR1_CLK_DIV_NUM` reader - Reserved"]
6pub type ADC_SAR1_CLK_DIV_NUM_R = crate::FieldReader;
7#[doc = "Field `ADC_SAR1_CLK_DIV_NUM` writer - Reserved"]
8pub type ADC_SAR1_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `ADC_SAR2_CLK_DIV_NUM` reader - Reserved"]
10pub type ADC_SAR2_CLK_DIV_NUM_R = crate::FieldReader;
11#[doc = "Field `ADC_SAR2_CLK_DIV_NUM` writer - Reserved"]
12pub type ADC_SAR2_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `PVT_CLK_DIV_NUM` reader - Reserved"]
14pub type PVT_CLK_DIV_NUM_R = crate::FieldReader;
15#[doc = "Field `PVT_CLK_DIV_NUM` writer - Reserved"]
16pub type PVT_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17#[doc = "Field `PVT_CLK_EN` reader - Reserved"]
18pub type PVT_CLK_EN_R = crate::BitReader;
19#[doc = "Field `PVT_CLK_EN` writer - Reserved"]
20pub type PVT_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bits 0:7 - Reserved"]
23    #[inline(always)]
24    pub fn adc_sar1_clk_div_num(&self) -> ADC_SAR1_CLK_DIV_NUM_R {
25        ADC_SAR1_CLK_DIV_NUM_R::new((self.bits & 0xff) as u8)
26    }
27    #[doc = "Bits 8:15 - Reserved"]
28    #[inline(always)]
29    pub fn adc_sar2_clk_div_num(&self) -> ADC_SAR2_CLK_DIV_NUM_R {
30        ADC_SAR2_CLK_DIV_NUM_R::new(((self.bits >> 8) & 0xff) as u8)
31    }
32    #[doc = "Bits 16:23 - Reserved"]
33    #[inline(always)]
34    pub fn pvt_clk_div_num(&self) -> PVT_CLK_DIV_NUM_R {
35        PVT_CLK_DIV_NUM_R::new(((self.bits >> 16) & 0xff) as u8)
36    }
37    #[doc = "Bit 24 - Reserved"]
38    #[inline(always)]
39    pub fn pvt_clk_en(&self) -> PVT_CLK_EN_R {
40        PVT_CLK_EN_R::new(((self.bits >> 24) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("PERI_CLK_CTRL24")
47            .field(
48                "adc_sar1_clk_div_num",
49                &format_args!("{}", self.adc_sar1_clk_div_num().bits()),
50            )
51            .field(
52                "adc_sar2_clk_div_num",
53                &format_args!("{}", self.adc_sar2_clk_div_num().bits()),
54            )
55            .field(
56                "pvt_clk_div_num",
57                &format_args!("{}", self.pvt_clk_div_num().bits()),
58            )
59            .field("pvt_clk_en", &format_args!("{}", self.pvt_clk_en().bit()))
60            .finish()
61    }
62}
63#[cfg(feature = "impl-register-debug")]
64impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL24_SPEC> {
65    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
66        core::fmt::Debug::fmt(&self.read(), f)
67    }
68}
69impl W {
70    #[doc = "Bits 0:7 - Reserved"]
71    #[inline(always)]
72    #[must_use]
73    pub fn adc_sar1_clk_div_num(&mut self) -> ADC_SAR1_CLK_DIV_NUM_W<PERI_CLK_CTRL24_SPEC> {
74        ADC_SAR1_CLK_DIV_NUM_W::new(self, 0)
75    }
76    #[doc = "Bits 8:15 - Reserved"]
77    #[inline(always)]
78    #[must_use]
79    pub fn adc_sar2_clk_div_num(&mut self) -> ADC_SAR2_CLK_DIV_NUM_W<PERI_CLK_CTRL24_SPEC> {
80        ADC_SAR2_CLK_DIV_NUM_W::new(self, 8)
81    }
82    #[doc = "Bits 16:23 - Reserved"]
83    #[inline(always)]
84    #[must_use]
85    pub fn pvt_clk_div_num(&mut self) -> PVT_CLK_DIV_NUM_W<PERI_CLK_CTRL24_SPEC> {
86        PVT_CLK_DIV_NUM_W::new(self, 16)
87    }
88    #[doc = "Bit 24 - Reserved"]
89    #[inline(always)]
90    #[must_use]
91    pub fn pvt_clk_en(&mut self) -> PVT_CLK_EN_W<PERI_CLK_CTRL24_SPEC> {
92        PVT_CLK_EN_W::new(self, 24)
93    }
94}
95#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl24::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl24::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
96pub struct PERI_CLK_CTRL24_SPEC;
97impl crate::RegisterSpec for PERI_CLK_CTRL24_SPEC {
98    type Ux = u32;
99}
100#[doc = "`read()` method returns [`peri_clk_ctrl24::R`](R) reader structure"]
101impl crate::Readable for PERI_CLK_CTRL24_SPEC {}
102#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl24::W`](W) writer structure"]
103impl crate::Writable for PERI_CLK_CTRL24_SPEC {
104    type Safety = crate::Unsafe;
105    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
106    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
107}
108#[doc = "`reset()` method sets PERI_CLK_CTRL24 to value 0x0404"]
109impl crate::Resettable for PERI_CLK_CTRL24_SPEC {
110    const RESET_VALUE: u32 = 0x0404;
111}
esp32p4/hp_sys_clkrst/peri_clk_ctrl24.rs

esp32p4/hp_sys_clkrst/
peri_clk_ctrl24.rs
