esp32p4/hp_sys_clkrst/
peri_clk_ctrl13.rs1#[doc = "Register `PERI_CLK_CTRL13` reader"]
2pub type R = crate::R<PERI_CLK_CTRL13_SPEC>;
3#[doc = "Register `PERI_CLK_CTRL13` writer"]
4pub type W = crate::W<PERI_CLK_CTRL13_SPEC>;
5#[doc = "Field `I2S0_RX_DIV_Z` reader - Reserved"]
6pub type I2S0_RX_DIV_Z_R = crate::FieldReader<u16>;
7#[doc = "Field `I2S0_RX_DIV_Z` writer - Reserved"]
8pub type I2S0_RX_DIV_Z_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
9#[doc = "Field `I2S0_RX_DIV_YN1` reader - Reserved"]
10pub type I2S0_RX_DIV_YN1_R = crate::BitReader;
11#[doc = "Field `I2S0_RX_DIV_YN1` writer - Reserved"]
12pub type I2S0_RX_DIV_YN1_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `I2S0_TX_CLK_EN` reader - Reserved"]
14pub type I2S0_TX_CLK_EN_R = crate::BitReader;
15#[doc = "Field `I2S0_TX_CLK_EN` writer - Reserved"]
16pub type I2S0_TX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `I2S0_TX_CLK_SRC_SEL` reader - Reserved"]
18pub type I2S0_TX_CLK_SRC_SEL_R = crate::FieldReader;
19#[doc = "Field `I2S0_TX_CLK_SRC_SEL` writer - Reserved"]
20pub type I2S0_TX_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `I2S0_TX_DIV_N` reader - Reserved"]
22pub type I2S0_TX_DIV_N_R = crate::FieldReader;
23#[doc = "Field `I2S0_TX_DIV_N` writer - Reserved"]
24pub type I2S0_TX_DIV_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
25#[doc = "Field `I2S0_TX_DIV_X` reader - Reserved"]
26pub type I2S0_TX_DIV_X_R = crate::FieldReader<u16>;
27#[doc = "Field `I2S0_TX_DIV_X` writer - Reserved"]
28pub type I2S0_TX_DIV_X_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
29impl R {
30 #[doc = "Bits 0:8 - Reserved"]
31 #[inline(always)]
32 pub fn i2s0_rx_div_z(&self) -> I2S0_RX_DIV_Z_R {
33 I2S0_RX_DIV_Z_R::new((self.bits & 0x01ff) as u16)
34 }
35 #[doc = "Bit 9 - Reserved"]
36 #[inline(always)]
37 pub fn i2s0_rx_div_yn1(&self) -> I2S0_RX_DIV_YN1_R {
38 I2S0_RX_DIV_YN1_R::new(((self.bits >> 9) & 1) != 0)
39 }
40 #[doc = "Bit 10 - Reserved"]
41 #[inline(always)]
42 pub fn i2s0_tx_clk_en(&self) -> I2S0_TX_CLK_EN_R {
43 I2S0_TX_CLK_EN_R::new(((self.bits >> 10) & 1) != 0)
44 }
45 #[doc = "Bits 11:12 - Reserved"]
46 #[inline(always)]
47 pub fn i2s0_tx_clk_src_sel(&self) -> I2S0_TX_CLK_SRC_SEL_R {
48 I2S0_TX_CLK_SRC_SEL_R::new(((self.bits >> 11) & 3) as u8)
49 }
50 #[doc = "Bits 13:20 - Reserved"]
51 #[inline(always)]
52 pub fn i2s0_tx_div_n(&self) -> I2S0_TX_DIV_N_R {
53 I2S0_TX_DIV_N_R::new(((self.bits >> 13) & 0xff) as u8)
54 }
55 #[doc = "Bits 21:29 - Reserved"]
56 #[inline(always)]
57 pub fn i2s0_tx_div_x(&self) -> I2S0_TX_DIV_X_R {
58 I2S0_TX_DIV_X_R::new(((self.bits >> 21) & 0x01ff) as u16)
59 }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64 f.debug_struct("PERI_CLK_CTRL13")
65 .field(
66 "i2s0_rx_div_z",
67 &format_args!("{}", self.i2s0_rx_div_z().bits()),
68 )
69 .field(
70 "i2s0_rx_div_yn1",
71 &format_args!("{}", self.i2s0_rx_div_yn1().bit()),
72 )
73 .field(
74 "i2s0_tx_clk_en",
75 &format_args!("{}", self.i2s0_tx_clk_en().bit()),
76 )
77 .field(
78 "i2s0_tx_clk_src_sel",
79 &format_args!("{}", self.i2s0_tx_clk_src_sel().bits()),
80 )
81 .field(
82 "i2s0_tx_div_n",
83 &format_args!("{}", self.i2s0_tx_div_n().bits()),
84 )
85 .field(
86 "i2s0_tx_div_x",
87 &format_args!("{}", self.i2s0_tx_div_x().bits()),
88 )
89 .finish()
90 }
91}
92#[cfg(feature = "impl-register-debug")]
93impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL13_SPEC> {
94 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
95 core::fmt::Debug::fmt(&self.read(), f)
96 }
97}
98impl W {
99 #[doc = "Bits 0:8 - Reserved"]
100 #[inline(always)]
101 #[must_use]
102 pub fn i2s0_rx_div_z(&mut self) -> I2S0_RX_DIV_Z_W<PERI_CLK_CTRL13_SPEC> {
103 I2S0_RX_DIV_Z_W::new(self, 0)
104 }
105 #[doc = "Bit 9 - Reserved"]
106 #[inline(always)]
107 #[must_use]
108 pub fn i2s0_rx_div_yn1(&mut self) -> I2S0_RX_DIV_YN1_W<PERI_CLK_CTRL13_SPEC> {
109 I2S0_RX_DIV_YN1_W::new(self, 9)
110 }
111 #[doc = "Bit 10 - Reserved"]
112 #[inline(always)]
113 #[must_use]
114 pub fn i2s0_tx_clk_en(&mut self) -> I2S0_TX_CLK_EN_W<PERI_CLK_CTRL13_SPEC> {
115 I2S0_TX_CLK_EN_W::new(self, 10)
116 }
117 #[doc = "Bits 11:12 - Reserved"]
118 #[inline(always)]
119 #[must_use]
120 pub fn i2s0_tx_clk_src_sel(&mut self) -> I2S0_TX_CLK_SRC_SEL_W<PERI_CLK_CTRL13_SPEC> {
121 I2S0_TX_CLK_SRC_SEL_W::new(self, 11)
122 }
123 #[doc = "Bits 13:20 - Reserved"]
124 #[inline(always)]
125 #[must_use]
126 pub fn i2s0_tx_div_n(&mut self) -> I2S0_TX_DIV_N_W<PERI_CLK_CTRL13_SPEC> {
127 I2S0_TX_DIV_N_W::new(self, 13)
128 }
129 #[doc = "Bits 21:29 - Reserved"]
130 #[inline(always)]
131 #[must_use]
132 pub fn i2s0_tx_div_x(&mut self) -> I2S0_TX_DIV_X_W<PERI_CLK_CTRL13_SPEC> {
133 I2S0_TX_DIV_X_W::new(self, 21)
134 }
135}
136#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
137pub struct PERI_CLK_CTRL13_SPEC;
138impl crate::RegisterSpec for PERI_CLK_CTRL13_SPEC {
139 type Ux = u32;
140}
141#[doc = "`read()` method returns [`peri_clk_ctrl13::R`](R) reader structure"]
142impl crate::Readable for PERI_CLK_CTRL13_SPEC {}
143#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl13::W`](W) writer structure"]
144impl crate::Writable for PERI_CLK_CTRL13_SPEC {
145 type Safety = crate::Unsafe;
146 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
147 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
148}
149#[doc = "`reset()` method sets PERI_CLK_CTRL13 to value 0"]
150impl crate::Resettable for PERI_CLK_CTRL13_SPEC {
151 const RESET_VALUE: u32 = 0;
152}