esp32p4/h264_dma/out_ch/
int_ena.rs1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `OUT_DONE` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."]
6pub type OUT_DONE_R = crate::BitReader;
7#[doc = "Field `OUT_DONE` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."]
8pub type OUT_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `OUT_EOF` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."]
10pub type OUT_EOF_R = crate::BitReader;
11#[doc = "Field `OUT_EOF` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."]
12pub type OUT_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `OUT_DSCR_ERR` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."]
14pub type OUT_DSCR_ERR_R = crate::BitReader;
15#[doc = "Field `OUT_DSCR_ERR` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."]
16pub type OUT_DSCR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `OUT_TOTAL_EOF` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."]
18pub type OUT_TOTAL_EOF_R = crate::BitReader;
19#[doc = "Field `OUT_TOTAL_EOF` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."]
20pub type OUT_TOTAL_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `OUTFIFO_OVF_L1` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."]
22pub type OUTFIFO_OVF_L1_R = crate::BitReader;
23#[doc = "Field `OUTFIFO_OVF_L1` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."]
24pub type OUTFIFO_OVF_L1_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `OUTFIFO_UDF_L1` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."]
26pub type OUTFIFO_UDF_L1_R = crate::BitReader;
27#[doc = "Field `OUTFIFO_UDF_L1` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."]
28pub type OUTFIFO_UDF_L1_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `OUTFIFO_OVF_L2` reader - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."]
30pub type OUTFIFO_OVF_L2_R = crate::BitReader;
31#[doc = "Field `OUTFIFO_OVF_L2` writer - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."]
32pub type OUTFIFO_OVF_L2_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `OUTFIFO_UDF_L2` reader - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."]
34pub type OUTFIFO_UDF_L2_R = crate::BitReader;
35#[doc = "Field `OUTFIFO_UDF_L2` writer - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."]
36pub type OUTFIFO_UDF_L2_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `OUT_DSCR_TASK_OVF` reader - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."]
38pub type OUT_DSCR_TASK_OVF_R = crate::BitReader;
39#[doc = "Field `OUT_DSCR_TASK_OVF` writer - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."]
40pub type OUT_DSCR_TASK_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42 #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."]
43 #[inline(always)]
44 pub fn out_done(&self) -> OUT_DONE_R {
45 OUT_DONE_R::new((self.bits & 1) != 0)
46 }
47 #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."]
48 #[inline(always)]
49 pub fn out_eof(&self) -> OUT_EOF_R {
50 OUT_EOF_R::new(((self.bits >> 1) & 1) != 0)
51 }
52 #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."]
53 #[inline(always)]
54 pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R {
55 OUT_DSCR_ERR_R::new(((self.bits >> 2) & 1) != 0)
56 }
57 #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."]
58 #[inline(always)]
59 pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R {
60 OUT_TOTAL_EOF_R::new(((self.bits >> 3) & 1) != 0)
61 }
62 #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."]
63 #[inline(always)]
64 pub fn outfifo_ovf_l1(&self) -> OUTFIFO_OVF_L1_R {
65 OUTFIFO_OVF_L1_R::new(((self.bits >> 4) & 1) != 0)
66 }
67 #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."]
68 #[inline(always)]
69 pub fn outfifo_udf_l1(&self) -> OUTFIFO_UDF_L1_R {
70 OUTFIFO_UDF_L1_R::new(((self.bits >> 5) & 1) != 0)
71 }
72 #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."]
73 #[inline(always)]
74 pub fn outfifo_ovf_l2(&self) -> OUTFIFO_OVF_L2_R {
75 OUTFIFO_OVF_L2_R::new(((self.bits >> 6) & 1) != 0)
76 }
77 #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."]
78 #[inline(always)]
79 pub fn outfifo_udf_l2(&self) -> OUTFIFO_UDF_L2_R {
80 OUTFIFO_UDF_L2_R::new(((self.bits >> 7) & 1) != 0)
81 }
82 #[doc = "Bit 8 - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."]
83 #[inline(always)]
84 pub fn out_dscr_task_ovf(&self) -> OUT_DSCR_TASK_OVF_R {
85 OUT_DSCR_TASK_OVF_R::new(((self.bits >> 8) & 1) != 0)
86 }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91 f.debug_struct("INT_ENA")
92 .field("out_done", &format_args!("{}", self.out_done().bit()))
93 .field("out_eof", &format_args!("{}", self.out_eof().bit()))
94 .field(
95 "out_dscr_err",
96 &format_args!("{}", self.out_dscr_err().bit()),
97 )
98 .field(
99 "out_total_eof",
100 &format_args!("{}", self.out_total_eof().bit()),
101 )
102 .field(
103 "outfifo_ovf_l1",
104 &format_args!("{}", self.outfifo_ovf_l1().bit()),
105 )
106 .field(
107 "outfifo_udf_l1",
108 &format_args!("{}", self.outfifo_udf_l1().bit()),
109 )
110 .field(
111 "outfifo_ovf_l2",
112 &format_args!("{}", self.outfifo_ovf_l2().bit()),
113 )
114 .field(
115 "outfifo_udf_l2",
116 &format_args!("{}", self.outfifo_udf_l2().bit()),
117 )
118 .field(
119 "out_dscr_task_ovf",
120 &format_args!("{}", self.out_dscr_task_ovf().bit()),
121 )
122 .finish()
123 }
124}
125#[cfg(feature = "impl-register-debug")]
126impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
127 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
128 core::fmt::Debug::fmt(&self.read(), f)
129 }
130}
131impl W {
132 #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."]
133 #[inline(always)]
134 #[must_use]
135 pub fn out_done(&mut self) -> OUT_DONE_W<INT_ENA_SPEC> {
136 OUT_DONE_W::new(self, 0)
137 }
138 #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."]
139 #[inline(always)]
140 #[must_use]
141 pub fn out_eof(&mut self) -> OUT_EOF_W<INT_ENA_SPEC> {
142 OUT_EOF_W::new(self, 1)
143 }
144 #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."]
145 #[inline(always)]
146 #[must_use]
147 pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<INT_ENA_SPEC> {
148 OUT_DSCR_ERR_W::new(self, 2)
149 }
150 #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."]
151 #[inline(always)]
152 #[must_use]
153 pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<INT_ENA_SPEC> {
154 OUT_TOTAL_EOF_W::new(self, 3)
155 }
156 #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."]
157 #[inline(always)]
158 #[must_use]
159 pub fn outfifo_ovf_l1(&mut self) -> OUTFIFO_OVF_L1_W<INT_ENA_SPEC> {
160 OUTFIFO_OVF_L1_W::new(self, 4)
161 }
162 #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."]
163 #[inline(always)]
164 #[must_use]
165 pub fn outfifo_udf_l1(&mut self) -> OUTFIFO_UDF_L1_W<INT_ENA_SPEC> {
166 OUTFIFO_UDF_L1_W::new(self, 5)
167 }
168 #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."]
169 #[inline(always)]
170 #[must_use]
171 pub fn outfifo_ovf_l2(&mut self) -> OUTFIFO_OVF_L2_W<INT_ENA_SPEC> {
172 OUTFIFO_OVF_L2_W::new(self, 6)
173 }
174 #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."]
175 #[inline(always)]
176 #[must_use]
177 pub fn outfifo_udf_l2(&mut self) -> OUTFIFO_UDF_L2_W<INT_ENA_SPEC> {
178 OUTFIFO_UDF_L2_W::new(self, 7)
179 }
180 #[doc = "Bit 8 - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."]
181 #[inline(always)]
182 #[must_use]
183 pub fn out_dscr_task_ovf(&mut self) -> OUT_DSCR_TASK_OVF_W<INT_ENA_SPEC> {
184 OUT_DSCR_TASK_OVF_W::new(self, 8)
185 }
186}
187#[doc = "TX CHx interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
188pub struct INT_ENA_SPEC;
189impl crate::RegisterSpec for INT_ENA_SPEC {
190 type Ux = u32;
191}
192#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
193impl crate::Readable for INT_ENA_SPEC {}
194#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
195impl crate::Writable for INT_ENA_SPEC {
196 type Safety = crate::Unsafe;
197 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
198 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
199}
200#[doc = "`reset()` method sets INT_ENA to value 0"]
201impl crate::Resettable for INT_ENA_SPEC {
202 const RESET_VALUE: u32 = 0;
203}