esp32p4/h264_dma/
inter_mem_end_addr0.rs

1#[doc = "Register `INTER_MEM_END_ADDR0` reader"]
2pub type R = crate::R<INTER_MEM_END_ADDR0_SPEC>;
3#[doc = "Register `INTER_MEM_END_ADDR0` writer"]
4pub type W = crate::W<INTER_MEM_END_ADDR0_SPEC>;
5#[doc = "Field `ACCESS_INTER_MEM_END_ADDR0` reader - The end address of accessible address space. The access address beyond this range would lead to descriptor error."]
6pub type ACCESS_INTER_MEM_END_ADDR0_R = crate::FieldReader<u32>;
7#[doc = "Field `ACCESS_INTER_MEM_END_ADDR0` writer - The end address of accessible address space. The access address beyond this range would lead to descriptor error."]
8pub type ACCESS_INTER_MEM_END_ADDR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."]
11    #[inline(always)]
12    pub fn access_inter_mem_end_addr0(&self) -> ACCESS_INTER_MEM_END_ADDR0_R {
13        ACCESS_INTER_MEM_END_ADDR0_R::new(self.bits)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("INTER_MEM_END_ADDR0")
20            .field(
21                "access_inter_mem_end_addr0",
22                &format_args!("{}", self.access_inter_mem_end_addr0().bits()),
23            )
24            .finish()
25    }
26}
27#[cfg(feature = "impl-register-debug")]
28impl core::fmt::Debug for crate::generic::Reg<INTER_MEM_END_ADDR0_SPEC> {
29    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
30        core::fmt::Debug::fmt(&self.read(), f)
31    }
32}
33impl W {
34    #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."]
35    #[inline(always)]
36    #[must_use]
37    pub fn access_inter_mem_end_addr0(
38        &mut self,
39    ) -> ACCESS_INTER_MEM_END_ADDR0_W<INTER_MEM_END_ADDR0_SPEC> {
40        ACCESS_INTER_MEM_END_ADDR0_W::new(self, 0)
41    }
42}
43#[doc = "end address of inter memory range0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inter_mem_end_addr0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inter_mem_end_addr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
44pub struct INTER_MEM_END_ADDR0_SPEC;
45impl crate::RegisterSpec for INTER_MEM_END_ADDR0_SPEC {
46    type Ux = u32;
47}
48#[doc = "`read()` method returns [`inter_mem_end_addr0::R`](R) reader structure"]
49impl crate::Readable for INTER_MEM_END_ADDR0_SPEC {}
50#[doc = "`write(|w| ..)` method takes [`inter_mem_end_addr0::W`](W) writer structure"]
51impl crate::Writable for INTER_MEM_END_ADDR0_SPEC {
52    type Safety = crate::Unsafe;
53    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
54    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
55}
56#[doc = "`reset()` method sets INTER_MEM_END_ADDR0 to value 0x8fff_ffff"]
57impl crate::Resettable for INTER_MEM_END_ADDR0_SPEC {
58    const RESET_VALUE: u32 = 0x8fff_ffff;
59}
esp32p4/h264_dma/inter_mem_end_addr0.rs

esp32p4/h264_dma/
inter_mem_end_addr0.rs
