1#[doc = "Register `CONF` reader"]
2pub type R = crate::R<CONF_SPEC>;
3#[doc = "Register `CONF` writer"]
4pub type W = crate::W<CONF_SPEC>;
5#[doc = "Field `CLK_EN` reader - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"]
6pub type CLK_EN_R = crate::BitReader;
7#[doc = "Field `CLK_EN` writer - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"]
8pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `REC_RAM_CLK_EN2` reader - Configures whether or not to open the clock gate for rec ram2.\\\\0: Open the clock gate only when application writes or reads rec ram2\\\\1: Force open the clock gate for rec ram2"]
10pub type REC_RAM_CLK_EN2_R = crate::BitReader;
11#[doc = "Field `REC_RAM_CLK_EN2` writer - Configures whether or not to open the clock gate for rec ram2.\\\\0: Open the clock gate only when application writes or reads rec ram2\\\\1: Force open the clock gate for rec ram2"]
12pub type REC_RAM_CLK_EN2_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `REC_RAM_CLK_EN1` reader - Configures whether or not to open the clock gate for rec ram1.\\\\0: Open the clock gate only when application writes or reads rec ram1\\\\1: Force open the clock gate for rec ram1"]
14pub type REC_RAM_CLK_EN1_R = crate::BitReader;
15#[doc = "Field `REC_RAM_CLK_EN1` writer - Configures whether or not to open the clock gate for rec ram1.\\\\0: Open the clock gate only when application writes or reads rec ram1\\\\1: Force open the clock gate for rec ram1"]
16pub type REC_RAM_CLK_EN1_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `QUANT_RAM_CLK_EN2` reader - Configures whether or not to open the clock gate for quant ram2.\\\\0: Open the clock gate only when application writes or reads quant ram2\\\\1: Force open the clock gate for quant ram2"]
18pub type QUANT_RAM_CLK_EN2_R = crate::BitReader;
19#[doc = "Field `QUANT_RAM_CLK_EN2` writer - Configures whether or not to open the clock gate for quant ram2.\\\\0: Open the clock gate only when application writes or reads quant ram2\\\\1: Force open the clock gate for quant ram2"]
20pub type QUANT_RAM_CLK_EN2_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `QUANT_RAM_CLK_EN1` reader - Configures whether or not to open the clock gate for quant ram1.\\\\0: Open the clock gate only when application writes or reads quant ram1\\\\1: Force open the clock gate for quant ram1"]
22pub type QUANT_RAM_CLK_EN1_R = crate::BitReader;
23#[doc = "Field `QUANT_RAM_CLK_EN1` writer - Configures whether or not to open the clock gate for quant ram1.\\\\0: Open the clock gate only when application writes or reads quant ram1\\\\1: Force open the clock gate for quant ram1"]
24pub type QUANT_RAM_CLK_EN1_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `PRE_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for pre ram.\\\\0: Open the clock gate only when application writes or reads pre ram\\\\1: Force open the clock gate for pre ram"]
26pub type PRE_RAM_CLK_EN_R = crate::BitReader;
27#[doc = "Field `PRE_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for pre ram.\\\\0: Open the clock gate only when application writes or reads pre ram\\\\1: Force open the clock gate for pre ram"]
28pub type PRE_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `MVD_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for mvd ram.\\\\0: Open the clock gate only when application writes or reads mvd ram\\\\1: Force open the clock gate for mvd ram"]
30pub type MVD_RAM_CLK_EN_R = crate::BitReader;
31#[doc = "Field `MVD_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for mvd ram.\\\\0: Open the clock gate only when application writes or reads mvd ram\\\\1: Force open the clock gate for mvd ram"]
32pub type MVD_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `MC_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for mc ram.\\\\0: Open the clock gate only when application writes or reads mc ram\\\\1: Force open the clock gate for mc ram"]
34pub type MC_RAM_CLK_EN_R = crate::BitReader;
35#[doc = "Field `MC_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for mc ram.\\\\0: Open the clock gate only when application writes or reads mc ram\\\\1: Force open the clock gate for mc ram"]
36pub type MC_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `REF_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for ref ram.\\\\0: Open the clock gate only when application writes or reads ref ram\\\\1: Force open the clock gate for ref ram"]
38pub type REF_RAM_CLK_EN_R = crate::BitReader;
39#[doc = "Field `REF_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for ref ram.\\\\0: Open the clock gate only when application writes or reads ref ram\\\\1: Force open the clock gate for ref ram"]
40pub type REF_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `I4X4_REF_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for i4x4_mode ram.\\\\0: Open the clock gate only when application writes or reads i4x4_mode ram\\\\1: Force open the clock gate for i4x4_mode ram"]
42pub type I4X4_REF_RAM_CLK_EN_R = crate::BitReader;
43#[doc = "Field `I4X4_REF_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for i4x4_mode ram.\\\\0: Open the clock gate only when application writes or reads i4x4_mode ram\\\\1: Force open the clock gate for i4x4_mode ram"]
44pub type I4X4_REF_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `IME_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for ime ram.\\\\0: Open the clock gate only when application writes or reads ime ram\\\\1: Force open the clock gate for ime ram"]
46pub type IME_RAM_CLK_EN_R = crate::BitReader;
47#[doc = "Field `IME_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for ime ram.\\\\0: Open the clock gate only when application writes or reads ime ram\\\\1: Force open the clock gate for ime ram"]
48pub type IME_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `FME_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for fme ram.\\\\0: Open the clock gate only when application writes or readsfme ram\\\\1: Force open the clock gate for fme ram"]
50pub type FME_RAM_CLK_EN_R = crate::BitReader;
51#[doc = "Field `FME_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for fme ram.\\\\0: Open the clock gate only when application writes or readsfme ram\\\\1: Force open the clock gate for fme ram"]
52pub type FME_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `FETCH_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for fetch ram.\\\\0: Open the clock gate only when application writes or reads fetch ram\\\\1: Force open the clock gate for fetch ram"]
54pub type FETCH_RAM_CLK_EN_R = crate::BitReader;
55#[doc = "Field `FETCH_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for fetch ram.\\\\0: Open the clock gate only when application writes or reads fetch ram\\\\1: Force open the clock gate for fetch ram"]
56pub type FETCH_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `DB_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for db ram.\\\\0: Open the clock gate only when application writes or reads db ram\\\\1: Force open the clock gate for db ram"]
58pub type DB_RAM_CLK_EN_R = crate::BitReader;
59#[doc = "Field `DB_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for db ram.\\\\0: Open the clock gate only when application writes or reads db ram\\\\1: Force open the clock gate for db ram"]
60pub type DB_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `CUR_MB_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for cur_mb ram.\\\\0: Open the clock gate only when application writes or reads cur_mb ram\\\\1: Force open the clock gate for cur_mb ram"]
62pub type CUR_MB_RAM_CLK_EN_R = crate::BitReader;
63#[doc = "Field `CUR_MB_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for cur_mb ram.\\\\0: Open the clock gate only when application writes or reads cur_mb ram\\\\1: Force open the clock gate for cur_mb ram"]
64pub type CUR_MB_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `CAVLC_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for cavlc ram.\\\\0: Open the clock gate only when application writes or reads cavlc ram\\\\1: Force open the clock gate for cavlc ram"]
66pub type CAVLC_RAM_CLK_EN_R = crate::BitReader;
67#[doc = "Field `CAVLC_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for cavlc ram.\\\\0: Open the clock gate only when application writes or reads cavlc ram\\\\1: Force open the clock gate for cavlc ram"]
68pub type CAVLC_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `IME_CLK_EN` reader - Configures whether or not to open the clock gate for ime.\\\\0: Open the clock gate only when ime work\\\\1: Force open the clock gate for ime"]
70pub type IME_CLK_EN_R = crate::BitReader;
71#[doc = "Field `IME_CLK_EN` writer - Configures whether or not to open the clock gate for ime.\\\\0: Open the clock gate only when ime work\\\\1: Force open the clock gate for ime"]
72pub type IME_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `FME_CLK_EN` reader - Configures whether or not to open the clock gate for fme.\\\\0: Open the clock gate only when fme work\\\\1: Force open the clock gate for fme"]
74pub type FME_CLK_EN_R = crate::BitReader;
75#[doc = "Field `FME_CLK_EN` writer - Configures whether or not to open the clock gate for fme.\\\\0: Open the clock gate only when fme work\\\\1: Force open the clock gate for fme"]
76pub type FME_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `MC_CLK_EN` reader - Configures whether or not to open the clock gate for mc.\\\\0: Open the clock gate only when mc work\\\\1: Force open the clock gate for mc"]
78pub type MC_CLK_EN_R = crate::BitReader;
79#[doc = "Field `MC_CLK_EN` writer - Configures whether or not to open the clock gate for mc.\\\\0: Open the clock gate only when mc work\\\\1: Force open the clock gate for mc"]
80pub type MC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `INTERPOLATOR_CLK_EN` reader - Configures whether or not to open the clock gate for interpolator.\\\\0: Open the clock gate only when interpolator work\\\\1: Force open the clock gate for interpolator"]
82pub type INTERPOLATOR_CLK_EN_R = crate::BitReader;
83#[doc = "Field `INTERPOLATOR_CLK_EN` writer - Configures whether or not to open the clock gate for interpolator.\\\\0: Open the clock gate only when interpolator work\\\\1: Force open the clock gate for interpolator"]
84pub type INTERPOLATOR_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `DB_CLK_EN` reader - Configures whether or not to open the clock gate for deblocking filter.\\\\0: Open the clock gate only when deblocking filter work\\\\1: Force open the clock gate for deblocking filter"]
86pub type DB_CLK_EN_R = crate::BitReader;
87#[doc = "Field `DB_CLK_EN` writer - Configures whether or not to open the clock gate for deblocking filter.\\\\0: Open the clock gate only when deblocking filter work\\\\1: Force open the clock gate for deblocking filter"]
88pub type DB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `CLAVLC_CLK_EN` reader - Configures whether or not to open the clock gate for cavlc.\\\\0: Open the clock gate only when cavlc work\\\\1: Force open the clock gate for cavlc"]
90pub type CLAVLC_CLK_EN_R = crate::BitReader;
91#[doc = "Field `CLAVLC_CLK_EN` writer - Configures whether or not to open the clock gate for cavlc.\\\\0: Open the clock gate only when cavlc work\\\\1: Force open the clock gate for cavlc"]
92pub type CLAVLC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `INTRA_CLK_EN` reader - Configures whether or not to open the clock gate for intra.\\\\0: Open the clock gate only when intra work\\\\1: Force open the clock gate for intra"]
94pub type INTRA_CLK_EN_R = crate::BitReader;
95#[doc = "Field `INTRA_CLK_EN` writer - Configures whether or not to open the clock gate for intra.\\\\0: Open the clock gate only when intra work\\\\1: Force open the clock gate for intra"]
96pub type INTRA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `DECI_CLK_EN` reader - Configures whether or not to open the clock gate for decimate.\\\\0: Open the clock gate only when decimate work\\\\1: Force open the clock gate for decimate"]
98pub type DECI_CLK_EN_R = crate::BitReader;
99#[doc = "Field `DECI_CLK_EN` writer - Configures whether or not to open the clock gate for decimate.\\\\0: Open the clock gate only when decimate work\\\\1: Force open the clock gate for decimate"]
100pub type DECI_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `BS_CLK_EN` reader - Configures whether or not to open the clock gate for bs buffer.\\\\0: Open the clock gate only when bs buffer work\\\\1: Force open the clock gate for bs buffer"]
102pub type BS_CLK_EN_R = crate::BitReader;
103#[doc = "Field `BS_CLK_EN` writer - Configures whether or not to open the clock gate for bs buffer.\\\\0: Open the clock gate only when bs buffer work\\\\1: Force open the clock gate for bs buffer"]
104pub type BS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
105#[doc = "Field `MV_MERGE_CLK_EN` reader - Configures whether or not to open the clock gate for mv merge.\\\\0: Open the clock gate only when mv merge work\\\\1: Force open the clock gate for mv merge"]
106pub type MV_MERGE_CLK_EN_R = crate::BitReader;
107#[doc = "Field `MV_MERGE_CLK_EN` writer - Configures whether or not to open the clock gate for mv merge.\\\\0: Open the clock gate only when mv merge work\\\\1: Force open the clock gate for mv merge"]
108pub type MV_MERGE_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
109impl R {
110 #[doc = "Bit 0 - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"]
111 #[inline(always)]
112 pub fn clk_en(&self) -> CLK_EN_R {
113 CLK_EN_R::new((self.bits & 1) != 0)
114 }
115 #[doc = "Bit 1 - Configures whether or not to open the clock gate for rec ram2.\\\\0: Open the clock gate only when application writes or reads rec ram2\\\\1: Force open the clock gate for rec ram2"]
116 #[inline(always)]
117 pub fn rec_ram_clk_en2(&self) -> REC_RAM_CLK_EN2_R {
118 REC_RAM_CLK_EN2_R::new(((self.bits >> 1) & 1) != 0)
119 }
120 #[doc = "Bit 2 - Configures whether or not to open the clock gate for rec ram1.\\\\0: Open the clock gate only when application writes or reads rec ram1\\\\1: Force open the clock gate for rec ram1"]
121 #[inline(always)]
122 pub fn rec_ram_clk_en1(&self) -> REC_RAM_CLK_EN1_R {
123 REC_RAM_CLK_EN1_R::new(((self.bits >> 2) & 1) != 0)
124 }
125 #[doc = "Bit 3 - Configures whether or not to open the clock gate for quant ram2.\\\\0: Open the clock gate only when application writes or reads quant ram2\\\\1: Force open the clock gate for quant ram2"]
126 #[inline(always)]
127 pub fn quant_ram_clk_en2(&self) -> QUANT_RAM_CLK_EN2_R {
128 QUANT_RAM_CLK_EN2_R::new(((self.bits >> 3) & 1) != 0)
129 }
130 #[doc = "Bit 4 - Configures whether or not to open the clock gate for quant ram1.\\\\0: Open the clock gate only when application writes or reads quant ram1\\\\1: Force open the clock gate for quant ram1"]
131 #[inline(always)]
132 pub fn quant_ram_clk_en1(&self) -> QUANT_RAM_CLK_EN1_R {
133 QUANT_RAM_CLK_EN1_R::new(((self.bits >> 4) & 1) != 0)
134 }
135 #[doc = "Bit 5 - Configures whether or not to open the clock gate for pre ram.\\\\0: Open the clock gate only when application writes or reads pre ram\\\\1: Force open the clock gate for pre ram"]
136 #[inline(always)]
137 pub fn pre_ram_clk_en(&self) -> PRE_RAM_CLK_EN_R {
138 PRE_RAM_CLK_EN_R::new(((self.bits >> 5) & 1) != 0)
139 }
140 #[doc = "Bit 6 - Configures whether or not to open the clock gate for mvd ram.\\\\0: Open the clock gate only when application writes or reads mvd ram\\\\1: Force open the clock gate for mvd ram"]
141 #[inline(always)]
142 pub fn mvd_ram_clk_en(&self) -> MVD_RAM_CLK_EN_R {
143 MVD_RAM_CLK_EN_R::new(((self.bits >> 6) & 1) != 0)
144 }
145 #[doc = "Bit 7 - Configures whether or not to open the clock gate for mc ram.\\\\0: Open the clock gate only when application writes or reads mc ram\\\\1: Force open the clock gate for mc ram"]
146 #[inline(always)]
147 pub fn mc_ram_clk_en(&self) -> MC_RAM_CLK_EN_R {
148 MC_RAM_CLK_EN_R::new(((self.bits >> 7) & 1) != 0)
149 }
150 #[doc = "Bit 8 - Configures whether or not to open the clock gate for ref ram.\\\\0: Open the clock gate only when application writes or reads ref ram\\\\1: Force open the clock gate for ref ram"]
151 #[inline(always)]
152 pub fn ref_ram_clk_en(&self) -> REF_RAM_CLK_EN_R {
153 REF_RAM_CLK_EN_R::new(((self.bits >> 8) & 1) != 0)
154 }
155 #[doc = "Bit 9 - Configures whether or not to open the clock gate for i4x4_mode ram.\\\\0: Open the clock gate only when application writes or reads i4x4_mode ram\\\\1: Force open the clock gate for i4x4_mode ram"]
156 #[inline(always)]
157 pub fn i4x4_ref_ram_clk_en(&self) -> I4X4_REF_RAM_CLK_EN_R {
158 I4X4_REF_RAM_CLK_EN_R::new(((self.bits >> 9) & 1) != 0)
159 }
160 #[doc = "Bit 10 - Configures whether or not to open the clock gate for ime ram.\\\\0: Open the clock gate only when application writes or reads ime ram\\\\1: Force open the clock gate for ime ram"]
161 #[inline(always)]
162 pub fn ime_ram_clk_en(&self) -> IME_RAM_CLK_EN_R {
163 IME_RAM_CLK_EN_R::new(((self.bits >> 10) & 1) != 0)
164 }
165 #[doc = "Bit 11 - Configures whether or not to open the clock gate for fme ram.\\\\0: Open the clock gate only when application writes or readsfme ram\\\\1: Force open the clock gate for fme ram"]
166 #[inline(always)]
167 pub fn fme_ram_clk_en(&self) -> FME_RAM_CLK_EN_R {
168 FME_RAM_CLK_EN_R::new(((self.bits >> 11) & 1) != 0)
169 }
170 #[doc = "Bit 12 - Configures whether or not to open the clock gate for fetch ram.\\\\0: Open the clock gate only when application writes or reads fetch ram\\\\1: Force open the clock gate for fetch ram"]
171 #[inline(always)]
172 pub fn fetch_ram_clk_en(&self) -> FETCH_RAM_CLK_EN_R {
173 FETCH_RAM_CLK_EN_R::new(((self.bits >> 12) & 1) != 0)
174 }
175 #[doc = "Bit 13 - Configures whether or not to open the clock gate for db ram.\\\\0: Open the clock gate only when application writes or reads db ram\\\\1: Force open the clock gate for db ram"]
176 #[inline(always)]
177 pub fn db_ram_clk_en(&self) -> DB_RAM_CLK_EN_R {
178 DB_RAM_CLK_EN_R::new(((self.bits >> 13) & 1) != 0)
179 }
180 #[doc = "Bit 14 - Configures whether or not to open the clock gate for cur_mb ram.\\\\0: Open the clock gate only when application writes or reads cur_mb ram\\\\1: Force open the clock gate for cur_mb ram"]
181 #[inline(always)]
182 pub fn cur_mb_ram_clk_en(&self) -> CUR_MB_RAM_CLK_EN_R {
183 CUR_MB_RAM_CLK_EN_R::new(((self.bits >> 14) & 1) != 0)
184 }
185 #[doc = "Bit 15 - Configures whether or not to open the clock gate for cavlc ram.\\\\0: Open the clock gate only when application writes or reads cavlc ram\\\\1: Force open the clock gate for cavlc ram"]
186 #[inline(always)]
187 pub fn cavlc_ram_clk_en(&self) -> CAVLC_RAM_CLK_EN_R {
188 CAVLC_RAM_CLK_EN_R::new(((self.bits >> 15) & 1) != 0)
189 }
190 #[doc = "Bit 16 - Configures whether or not to open the clock gate for ime.\\\\0: Open the clock gate only when ime work\\\\1: Force open the clock gate for ime"]
191 #[inline(always)]
192 pub fn ime_clk_en(&self) -> IME_CLK_EN_R {
193 IME_CLK_EN_R::new(((self.bits >> 16) & 1) != 0)
194 }
195 #[doc = "Bit 17 - Configures whether or not to open the clock gate for fme.\\\\0: Open the clock gate only when fme work\\\\1: Force open the clock gate for fme"]
196 #[inline(always)]
197 pub fn fme_clk_en(&self) -> FME_CLK_EN_R {
198 FME_CLK_EN_R::new(((self.bits >> 17) & 1) != 0)
199 }
200 #[doc = "Bit 18 - Configures whether or not to open the clock gate for mc.\\\\0: Open the clock gate only when mc work\\\\1: Force open the clock gate for mc"]
201 #[inline(always)]
202 pub fn mc_clk_en(&self) -> MC_CLK_EN_R {
203 MC_CLK_EN_R::new(((self.bits >> 18) & 1) != 0)
204 }
205 #[doc = "Bit 19 - Configures whether or not to open the clock gate for interpolator.\\\\0: Open the clock gate only when interpolator work\\\\1: Force open the clock gate for interpolator"]
206 #[inline(always)]
207 pub fn interpolator_clk_en(&self) -> INTERPOLATOR_CLK_EN_R {
208 INTERPOLATOR_CLK_EN_R::new(((self.bits >> 19) & 1) != 0)
209 }
210 #[doc = "Bit 20 - Configures whether or not to open the clock gate for deblocking filter.\\\\0: Open the clock gate only when deblocking filter work\\\\1: Force open the clock gate for deblocking filter"]
211 #[inline(always)]
212 pub fn db_clk_en(&self) -> DB_CLK_EN_R {
213 DB_CLK_EN_R::new(((self.bits >> 20) & 1) != 0)
214 }
215 #[doc = "Bit 21 - Configures whether or not to open the clock gate for cavlc.\\\\0: Open the clock gate only when cavlc work\\\\1: Force open the clock gate for cavlc"]
216 #[inline(always)]
217 pub fn clavlc_clk_en(&self) -> CLAVLC_CLK_EN_R {
218 CLAVLC_CLK_EN_R::new(((self.bits >> 21) & 1) != 0)
219 }
220 #[doc = "Bit 22 - Configures whether or not to open the clock gate for intra.\\\\0: Open the clock gate only when intra work\\\\1: Force open the clock gate for intra"]
221 #[inline(always)]
222 pub fn intra_clk_en(&self) -> INTRA_CLK_EN_R {
223 INTRA_CLK_EN_R::new(((self.bits >> 22) & 1) != 0)
224 }
225 #[doc = "Bit 23 - Configures whether or not to open the clock gate for decimate.\\\\0: Open the clock gate only when decimate work\\\\1: Force open the clock gate for decimate"]
226 #[inline(always)]
227 pub fn deci_clk_en(&self) -> DECI_CLK_EN_R {
228 DECI_CLK_EN_R::new(((self.bits >> 23) & 1) != 0)
229 }
230 #[doc = "Bit 24 - Configures whether or not to open the clock gate for bs buffer.\\\\0: Open the clock gate only when bs buffer work\\\\1: Force open the clock gate for bs buffer"]
231 #[inline(always)]
232 pub fn bs_clk_en(&self) -> BS_CLK_EN_R {
233 BS_CLK_EN_R::new(((self.bits >> 24) & 1) != 0)
234 }
235 #[doc = "Bit 25 - Configures whether or not to open the clock gate for mv merge.\\\\0: Open the clock gate only when mv merge work\\\\1: Force open the clock gate for mv merge"]
236 #[inline(always)]
237 pub fn mv_merge_clk_en(&self) -> MV_MERGE_CLK_EN_R {
238 MV_MERGE_CLK_EN_R::new(((self.bits >> 25) & 1) != 0)
239 }
240}
241#[cfg(feature = "impl-register-debug")]
242impl core::fmt::Debug for R {
243 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
244 f.debug_struct("CONF")
245 .field("clk_en", &format_args!("{}", self.clk_en().bit()))
246 .field(
247 "rec_ram_clk_en2",
248 &format_args!("{}", self.rec_ram_clk_en2().bit()),
249 )
250 .field(
251 "rec_ram_clk_en1",
252 &format_args!("{}", self.rec_ram_clk_en1().bit()),
253 )
254 .field(
255 "quant_ram_clk_en2",
256 &format_args!("{}", self.quant_ram_clk_en2().bit()),
257 )
258 .field(
259 "quant_ram_clk_en1",
260 &format_args!("{}", self.quant_ram_clk_en1().bit()),
261 )
262 .field(
263 "pre_ram_clk_en",
264 &format_args!("{}", self.pre_ram_clk_en().bit()),
265 )
266 .field(
267 "mvd_ram_clk_en",
268 &format_args!("{}", self.mvd_ram_clk_en().bit()),
269 )
270 .field(
271 "mc_ram_clk_en",
272 &format_args!("{}", self.mc_ram_clk_en().bit()),
273 )
274 .field(
275 "ref_ram_clk_en",
276 &format_args!("{}", self.ref_ram_clk_en().bit()),
277 )
278 .field(
279 "i4x4_ref_ram_clk_en",
280 &format_args!("{}", self.i4x4_ref_ram_clk_en().bit()),
281 )
282 .field(
283 "ime_ram_clk_en",
284 &format_args!("{}", self.ime_ram_clk_en().bit()),
285 )
286 .field(
287 "fme_ram_clk_en",
288 &format_args!("{}", self.fme_ram_clk_en().bit()),
289 )
290 .field(
291 "fetch_ram_clk_en",
292 &format_args!("{}", self.fetch_ram_clk_en().bit()),
293 )
294 .field(
295 "db_ram_clk_en",
296 &format_args!("{}", self.db_ram_clk_en().bit()),
297 )
298 .field(
299 "cur_mb_ram_clk_en",
300 &format_args!("{}", self.cur_mb_ram_clk_en().bit()),
301 )
302 .field(
303 "cavlc_ram_clk_en",
304 &format_args!("{}", self.cavlc_ram_clk_en().bit()),
305 )
306 .field("ime_clk_en", &format_args!("{}", self.ime_clk_en().bit()))
307 .field("fme_clk_en", &format_args!("{}", self.fme_clk_en().bit()))
308 .field("mc_clk_en", &format_args!("{}", self.mc_clk_en().bit()))
309 .field(
310 "interpolator_clk_en",
311 &format_args!("{}", self.interpolator_clk_en().bit()),
312 )
313 .field("db_clk_en", &format_args!("{}", self.db_clk_en().bit()))
314 .field(
315 "clavlc_clk_en",
316 &format_args!("{}", self.clavlc_clk_en().bit()),
317 )
318 .field(
319 "intra_clk_en",
320 &format_args!("{}", self.intra_clk_en().bit()),
321 )
322 .field("deci_clk_en", &format_args!("{}", self.deci_clk_en().bit()))
323 .field("bs_clk_en", &format_args!("{}", self.bs_clk_en().bit()))
324 .field(
325 "mv_merge_clk_en",
326 &format_args!("{}", self.mv_merge_clk_en().bit()),
327 )
328 .finish()
329 }
330}
331#[cfg(feature = "impl-register-debug")]
332impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
333 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
334 core::fmt::Debug::fmt(&self.read(), f)
335 }
336}
337impl W {
338 #[doc = "Bit 0 - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"]
339 #[inline(always)]
340 #[must_use]
341 pub fn clk_en(&mut self) -> CLK_EN_W<CONF_SPEC> {
342 CLK_EN_W::new(self, 0)
343 }
344 #[doc = "Bit 1 - Configures whether or not to open the clock gate for rec ram2.\\\\0: Open the clock gate only when application writes or reads rec ram2\\\\1: Force open the clock gate for rec ram2"]
345 #[inline(always)]
346 #[must_use]
347 pub fn rec_ram_clk_en2(&mut self) -> REC_RAM_CLK_EN2_W<CONF_SPEC> {
348 REC_RAM_CLK_EN2_W::new(self, 1)
349 }
350 #[doc = "Bit 2 - Configures whether or not to open the clock gate for rec ram1.\\\\0: Open the clock gate only when application writes or reads rec ram1\\\\1: Force open the clock gate for rec ram1"]
351 #[inline(always)]
352 #[must_use]
353 pub fn rec_ram_clk_en1(&mut self) -> REC_RAM_CLK_EN1_W<CONF_SPEC> {
354 REC_RAM_CLK_EN1_W::new(self, 2)
355 }
356 #[doc = "Bit 3 - Configures whether or not to open the clock gate for quant ram2.\\\\0: Open the clock gate only when application writes or reads quant ram2\\\\1: Force open the clock gate for quant ram2"]
357 #[inline(always)]
358 #[must_use]
359 pub fn quant_ram_clk_en2(&mut self) -> QUANT_RAM_CLK_EN2_W<CONF_SPEC> {
360 QUANT_RAM_CLK_EN2_W::new(self, 3)
361 }
362 #[doc = "Bit 4 - Configures whether or not to open the clock gate for quant ram1.\\\\0: Open the clock gate only when application writes or reads quant ram1\\\\1: Force open the clock gate for quant ram1"]
363 #[inline(always)]
364 #[must_use]
365 pub fn quant_ram_clk_en1(&mut self) -> QUANT_RAM_CLK_EN1_W<CONF_SPEC> {
366 QUANT_RAM_CLK_EN1_W::new(self, 4)
367 }
368 #[doc = "Bit 5 - Configures whether or not to open the clock gate for pre ram.\\\\0: Open the clock gate only when application writes or reads pre ram\\\\1: Force open the clock gate for pre ram"]
369 #[inline(always)]
370 #[must_use]
371 pub fn pre_ram_clk_en(&mut self) -> PRE_RAM_CLK_EN_W<CONF_SPEC> {
372 PRE_RAM_CLK_EN_W::new(self, 5)
373 }
374 #[doc = "Bit 6 - Configures whether or not to open the clock gate for mvd ram.\\\\0: Open the clock gate only when application writes or reads mvd ram\\\\1: Force open the clock gate for mvd ram"]
375 #[inline(always)]
376 #[must_use]
377 pub fn mvd_ram_clk_en(&mut self) -> MVD_RAM_CLK_EN_W<CONF_SPEC> {
378 MVD_RAM_CLK_EN_W::new(self, 6)
379 }
380 #[doc = "Bit 7 - Configures whether or not to open the clock gate for mc ram.\\\\0: Open the clock gate only when application writes or reads mc ram\\\\1: Force open the clock gate for mc ram"]
381 #[inline(always)]
382 #[must_use]
383 pub fn mc_ram_clk_en(&mut self) -> MC_RAM_CLK_EN_W<CONF_SPEC> {
384 MC_RAM_CLK_EN_W::new(self, 7)
385 }
386 #[doc = "Bit 8 - Configures whether or not to open the clock gate for ref ram.\\\\0: Open the clock gate only when application writes or reads ref ram\\\\1: Force open the clock gate for ref ram"]
387 #[inline(always)]
388 #[must_use]
389 pub fn ref_ram_clk_en(&mut self) -> REF_RAM_CLK_EN_W<CONF_SPEC> {
390 REF_RAM_CLK_EN_W::new(self, 8)
391 }
392 #[doc = "Bit 9 - Configures whether or not to open the clock gate for i4x4_mode ram.\\\\0: Open the clock gate only when application writes or reads i4x4_mode ram\\\\1: Force open the clock gate for i4x4_mode ram"]
393 #[inline(always)]
394 #[must_use]
395 pub fn i4x4_ref_ram_clk_en(&mut self) -> I4X4_REF_RAM_CLK_EN_W<CONF_SPEC> {
396 I4X4_REF_RAM_CLK_EN_W::new(self, 9)
397 }
398 #[doc = "Bit 10 - Configures whether or not to open the clock gate for ime ram.\\\\0: Open the clock gate only when application writes or reads ime ram\\\\1: Force open the clock gate for ime ram"]
399 #[inline(always)]
400 #[must_use]
401 pub fn ime_ram_clk_en(&mut self) -> IME_RAM_CLK_EN_W<CONF_SPEC> {
402 IME_RAM_CLK_EN_W::new(self, 10)
403 }
404 #[doc = "Bit 11 - Configures whether or not to open the clock gate for fme ram.\\\\0: Open the clock gate only when application writes or readsfme ram\\\\1: Force open the clock gate for fme ram"]
405 #[inline(always)]
406 #[must_use]
407 pub fn fme_ram_clk_en(&mut self) -> FME_RAM_CLK_EN_W<CONF_SPEC> {
408 FME_RAM_CLK_EN_W::new(self, 11)
409 }
410 #[doc = "Bit 12 - Configures whether or not to open the clock gate for fetch ram.\\\\0: Open the clock gate only when application writes or reads fetch ram\\\\1: Force open the clock gate for fetch ram"]
411 #[inline(always)]
412 #[must_use]
413 pub fn fetch_ram_clk_en(&mut self) -> FETCH_RAM_CLK_EN_W<CONF_SPEC> {
414 FETCH_RAM_CLK_EN_W::new(self, 12)
415 }
416 #[doc = "Bit 13 - Configures whether or not to open the clock gate for db ram.\\\\0: Open the clock gate only when application writes or reads db ram\\\\1: Force open the clock gate for db ram"]
417 #[inline(always)]
418 #[must_use]
419 pub fn db_ram_clk_en(&mut self) -> DB_RAM_CLK_EN_W<CONF_SPEC> {
420 DB_RAM_CLK_EN_W::new(self, 13)
421 }
422 #[doc = "Bit 14 - Configures whether or not to open the clock gate for cur_mb ram.\\\\0: Open the clock gate only when application writes or reads cur_mb ram\\\\1: Force open the clock gate for cur_mb ram"]
423 #[inline(always)]
424 #[must_use]
425 pub fn cur_mb_ram_clk_en(&mut self) -> CUR_MB_RAM_CLK_EN_W<CONF_SPEC> {
426 CUR_MB_RAM_CLK_EN_W::new(self, 14)
427 }
428 #[doc = "Bit 15 - Configures whether or not to open the clock gate for cavlc ram.\\\\0: Open the clock gate only when application writes or reads cavlc ram\\\\1: Force open the clock gate for cavlc ram"]
429 #[inline(always)]
430 #[must_use]
431 pub fn cavlc_ram_clk_en(&mut self) -> CAVLC_RAM_CLK_EN_W<CONF_SPEC> {
432 CAVLC_RAM_CLK_EN_W::new(self, 15)
433 }
434 #[doc = "Bit 16 - Configures whether or not to open the clock gate for ime.\\\\0: Open the clock gate only when ime work\\\\1: Force open the clock gate for ime"]
435 #[inline(always)]
436 #[must_use]
437 pub fn ime_clk_en(&mut self) -> IME_CLK_EN_W<CONF_SPEC> {
438 IME_CLK_EN_W::new(self, 16)
439 }
440 #[doc = "Bit 17 - Configures whether or not to open the clock gate for fme.\\\\0: Open the clock gate only when fme work\\\\1: Force open the clock gate for fme"]
441 #[inline(always)]
442 #[must_use]
443 pub fn fme_clk_en(&mut self) -> FME_CLK_EN_W<CONF_SPEC> {
444 FME_CLK_EN_W::new(self, 17)
445 }
446 #[doc = "Bit 18 - Configures whether or not to open the clock gate for mc.\\\\0: Open the clock gate only when mc work\\\\1: Force open the clock gate for mc"]
447 #[inline(always)]
448 #[must_use]
449 pub fn mc_clk_en(&mut self) -> MC_CLK_EN_W<CONF_SPEC> {
450 MC_CLK_EN_W::new(self, 18)
451 }
452 #[doc = "Bit 19 - Configures whether or not to open the clock gate for interpolator.\\\\0: Open the clock gate only when interpolator work\\\\1: Force open the clock gate for interpolator"]
453 #[inline(always)]
454 #[must_use]
455 pub fn interpolator_clk_en(&mut self) -> INTERPOLATOR_CLK_EN_W<CONF_SPEC> {
456 INTERPOLATOR_CLK_EN_W::new(self, 19)
457 }
458 #[doc = "Bit 20 - Configures whether or not to open the clock gate for deblocking filter.\\\\0: Open the clock gate only when deblocking filter work\\\\1: Force open the clock gate for deblocking filter"]
459 #[inline(always)]
460 #[must_use]
461 pub fn db_clk_en(&mut self) -> DB_CLK_EN_W<CONF_SPEC> {
462 DB_CLK_EN_W::new(self, 20)
463 }
464 #[doc = "Bit 21 - Configures whether or not to open the clock gate for cavlc.\\\\0: Open the clock gate only when cavlc work\\\\1: Force open the clock gate for cavlc"]
465 #[inline(always)]
466 #[must_use]
467 pub fn clavlc_clk_en(&mut self) -> CLAVLC_CLK_EN_W<CONF_SPEC> {
468 CLAVLC_CLK_EN_W::new(self, 21)
469 }
470 #[doc = "Bit 22 - Configures whether or not to open the clock gate for intra.\\\\0: Open the clock gate only when intra work\\\\1: Force open the clock gate for intra"]
471 #[inline(always)]
472 #[must_use]
473 pub fn intra_clk_en(&mut self) -> INTRA_CLK_EN_W<CONF_SPEC> {
474 INTRA_CLK_EN_W::new(self, 22)
475 }
476 #[doc = "Bit 23 - Configures whether or not to open the clock gate for decimate.\\\\0: Open the clock gate only when decimate work\\\\1: Force open the clock gate for decimate"]
477 #[inline(always)]
478 #[must_use]
479 pub fn deci_clk_en(&mut self) -> DECI_CLK_EN_W<CONF_SPEC> {
480 DECI_CLK_EN_W::new(self, 23)
481 }
482 #[doc = "Bit 24 - Configures whether or not to open the clock gate for bs buffer.\\\\0: Open the clock gate only when bs buffer work\\\\1: Force open the clock gate for bs buffer"]
483 #[inline(always)]
484 #[must_use]
485 pub fn bs_clk_en(&mut self) -> BS_CLK_EN_W<CONF_SPEC> {
486 BS_CLK_EN_W::new(self, 24)
487 }
488 #[doc = "Bit 25 - Configures whether or not to open the clock gate for mv merge.\\\\0: Open the clock gate only when mv merge work\\\\1: Force open the clock gate for mv merge"]
489 #[inline(always)]
490 #[must_use]
491 pub fn mv_merge_clk_en(&mut self) -> MV_MERGE_CLK_EN_W<CONF_SPEC> {
492 MV_MERGE_CLK_EN_W::new(self, 25)
493 }
494}
495#[doc = "General configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
496pub struct CONF_SPEC;
497impl crate::RegisterSpec for CONF_SPEC {
498 type Ux = u32;
499}
500#[doc = "`read()` method returns [`conf::R`](R) reader structure"]
501impl crate::Readable for CONF_SPEC {}
502#[doc = "`write(|w| ..)` method takes [`conf::W`](W) writer structure"]
503impl crate::Writable for CONF_SPEC {
504 type Safety = crate::Unsafe;
505 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
506 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
507}
508#[doc = "`reset()` method sets CONF to value 0"]
509impl crate::Resettable for CONF_SPEC {
510 const RESET_VALUE: u32 = 0;
511}