esp32p4/gpio_sd/
etm_event_ch_cfg.rs

1#[doc = "Register `ETM_EVENT_CH%s_CFG` reader"]
2pub type R = crate::R<ETM_EVENT_CH_CFG_SPEC>;
3#[doc = "Register `ETM_EVENT_CH%s_CFG` writer"]
4pub type W = crate::W<ETM_EVENT_CH_CFG_SPEC>;
5#[doc = "Field `ETM_CH0_EVENT_SEL` reader - Etm event channel select gpio."]
6pub type ETM_CH0_EVENT_SEL_R = crate::FieldReader;
7#[doc = "Field `ETM_CH0_EVENT_SEL` writer - Etm event channel select gpio."]
8pub type ETM_CH0_EVENT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `ETM_CH0_EVENT_EN` reader - Etm event send enable bit."]
10pub type ETM_CH0_EVENT_EN_R = crate::BitReader;
11#[doc = "Field `ETM_CH0_EVENT_EN` writer - Etm event send enable bit."]
12pub type ETM_CH0_EVENT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bits 0:5 - Etm event channel select gpio."]
15    #[inline(always)]
16    pub fn etm_ch0_event_sel(&self) -> ETM_CH0_EVENT_SEL_R {
17        ETM_CH0_EVENT_SEL_R::new((self.bits & 0x3f) as u8)
18    }
19    #[doc = "Bit 7 - Etm event send enable bit."]
20    #[inline(always)]
21    pub fn etm_ch0_event_en(&self) -> ETM_CH0_EVENT_EN_R {
22        ETM_CH0_EVENT_EN_R::new(((self.bits >> 7) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("ETM_EVENT_CH_CFG")
29            .field(
30                "etm_ch0_event_sel",
31                &format_args!("{}", self.etm_ch0_event_sel().bits()),
32            )
33            .field(
34                "etm_ch0_event_en",
35                &format_args!("{}", self.etm_ch0_event_en().bit()),
36            )
37            .finish()
38    }
39}
40#[cfg(feature = "impl-register-debug")]
41impl core::fmt::Debug for crate::generic::Reg<ETM_EVENT_CH_CFG_SPEC> {
42    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
43        core::fmt::Debug::fmt(&self.read(), f)
44    }
45}
46impl W {
47    #[doc = "Bits 0:5 - Etm event channel select gpio."]
48    #[inline(always)]
49    #[must_use]
50    pub fn etm_ch0_event_sel(&mut self) -> ETM_CH0_EVENT_SEL_W<ETM_EVENT_CH_CFG_SPEC> {
51        ETM_CH0_EVENT_SEL_W::new(self, 0)
52    }
53    #[doc = "Bit 7 - Etm event send enable bit."]
54    #[inline(always)]
55    #[must_use]
56    pub fn etm_ch0_event_en(&mut self) -> ETM_CH0_EVENT_EN_W<ETM_EVENT_CH_CFG_SPEC> {
57        ETM_CH0_EVENT_EN_W::new(self, 7)
58    }
59}
60#[doc = "Etm Config register of Channel%s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_event_ch_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_event_ch_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
61pub struct ETM_EVENT_CH_CFG_SPEC;
62impl crate::RegisterSpec for ETM_EVENT_CH_CFG_SPEC {
63    type Ux = u32;
64}
65#[doc = "`read()` method returns [`etm_event_ch_cfg::R`](R) reader structure"]
66impl crate::Readable for ETM_EVENT_CH_CFG_SPEC {}
67#[doc = "`write(|w| ..)` method takes [`etm_event_ch_cfg::W`](W) writer structure"]
68impl crate::Writable for ETM_EVENT_CH_CFG_SPEC {
69    type Safety = crate::Unsafe;
70    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
71    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72}
73#[doc = "`reset()` method sets ETM_EVENT_CH%s_CFG to value 0"]
74impl crate::Resettable for ETM_EVENT_CH_CFG_SPEC {
75    const RESET_VALUE: u32 = 0;
76}
esp32p4/gpio_sd/etm_event_ch_cfg.rs

esp32p4/gpio_sd/
etm_event_ch_cfg.rs
