esp32p4/cache/
sync_l1_cache_preload_int_st.rs

1#[doc = "Register `SYNC_L1_CACHE_PRELOAD_INT_ST` reader"]
2pub type R = crate::R<SYNC_L1_CACHE_PRELOAD_INT_ST_SPEC>;
3#[doc = "Field `L1_ICACHE0_PLD_DONE_INT_ST` reader - The bit indicates the status of the interrupt that occurs only when L1-ICache0 preload-operation is done."]
4pub type L1_ICACHE0_PLD_DONE_INT_ST_R = crate::BitReader;
5#[doc = "Field `L1_ICACHE1_PLD_DONE_INT_ST` reader - The bit indicates the status of the interrupt that occurs only when L1-ICache1 preload-operation is done."]
6pub type L1_ICACHE1_PLD_DONE_INT_ST_R = crate::BitReader;
7#[doc = "Field `L1_ICACHE2_PLD_DONE_INT_ST` reader - Reserved"]
8pub type L1_ICACHE2_PLD_DONE_INT_ST_R = crate::BitReader;
9#[doc = "Field `L1_ICACHE3_PLD_DONE_INT_ST` reader - Reserved"]
10pub type L1_ICACHE3_PLD_DONE_INT_ST_R = crate::BitReader;
11#[doc = "Field `L1_DCACHE_PLD_DONE_INT_ST` reader - The bit indicates the status of the interrupt that occurs only when L1-DCache preload-operation is done."]
12pub type L1_DCACHE_PLD_DONE_INT_ST_R = crate::BitReader;
13#[doc = "Field `SYNC_DONE_INT_ST` reader - The bit indicates the status of the interrupt that occurs only when Cache sync-operation is done."]
14pub type SYNC_DONE_INT_ST_R = crate::BitReader;
15#[doc = "Field `L1_ICACHE0_PLD_ERR_INT_ST` reader - The bit indicates the status of the interrupt of L1-ICache0 preload-operation error."]
16pub type L1_ICACHE0_PLD_ERR_INT_ST_R = crate::BitReader;
17#[doc = "Field `L1_ICACHE1_PLD_ERR_INT_ST` reader - The bit indicates the status of the interrupt of L1-ICache1 preload-operation error."]
18pub type L1_ICACHE1_PLD_ERR_INT_ST_R = crate::BitReader;
19#[doc = "Field `L1_ICACHE2_PLD_ERR_INT_ST` reader - Reserved"]
20pub type L1_ICACHE2_PLD_ERR_INT_ST_R = crate::BitReader;
21#[doc = "Field `L1_ICACHE3_PLD_ERR_INT_ST` reader - Reserved"]
22pub type L1_ICACHE3_PLD_ERR_INT_ST_R = crate::BitReader;
23#[doc = "Field `L1_DCACHE_PLD_ERR_INT_ST` reader - The bit indicates the status of the interrupt of L1-DCache preload-operation error."]
24pub type L1_DCACHE_PLD_ERR_INT_ST_R = crate::BitReader;
25#[doc = "Field `SYNC_ERR_INT_ST` reader - The bit indicates the status of the interrupt of Cache sync-operation error."]
26pub type SYNC_ERR_INT_ST_R = crate::BitReader;
27impl R {
28    #[doc = "Bit 0 - The bit indicates the status of the interrupt that occurs only when L1-ICache0 preload-operation is done."]
29    #[inline(always)]
30    pub fn l1_icache0_pld_done_int_st(&self) -> L1_ICACHE0_PLD_DONE_INT_ST_R {
31        L1_ICACHE0_PLD_DONE_INT_ST_R::new((self.bits & 1) != 0)
32    }
33    #[doc = "Bit 1 - The bit indicates the status of the interrupt that occurs only when L1-ICache1 preload-operation is done."]
34    #[inline(always)]
35    pub fn l1_icache1_pld_done_int_st(&self) -> L1_ICACHE1_PLD_DONE_INT_ST_R {
36        L1_ICACHE1_PLD_DONE_INT_ST_R::new(((self.bits >> 1) & 1) != 0)
37    }
38    #[doc = "Bit 2 - Reserved"]
39    #[inline(always)]
40    pub fn l1_icache2_pld_done_int_st(&self) -> L1_ICACHE2_PLD_DONE_INT_ST_R {
41        L1_ICACHE2_PLD_DONE_INT_ST_R::new(((self.bits >> 2) & 1) != 0)
42    }
43    #[doc = "Bit 3 - Reserved"]
44    #[inline(always)]
45    pub fn l1_icache3_pld_done_int_st(&self) -> L1_ICACHE3_PLD_DONE_INT_ST_R {
46        L1_ICACHE3_PLD_DONE_INT_ST_R::new(((self.bits >> 3) & 1) != 0)
47    }
48    #[doc = "Bit 4 - The bit indicates the status of the interrupt that occurs only when L1-DCache preload-operation is done."]
49    #[inline(always)]
50    pub fn l1_dcache_pld_done_int_st(&self) -> L1_DCACHE_PLD_DONE_INT_ST_R {
51        L1_DCACHE_PLD_DONE_INT_ST_R::new(((self.bits >> 4) & 1) != 0)
52    }
53    #[doc = "Bit 6 - The bit indicates the status of the interrupt that occurs only when Cache sync-operation is done."]
54    #[inline(always)]
55    pub fn sync_done_int_st(&self) -> SYNC_DONE_INT_ST_R {
56        SYNC_DONE_INT_ST_R::new(((self.bits >> 6) & 1) != 0)
57    }
58    #[doc = "Bit 7 - The bit indicates the status of the interrupt of L1-ICache0 preload-operation error."]
59    #[inline(always)]
60    pub fn l1_icache0_pld_err_int_st(&self) -> L1_ICACHE0_PLD_ERR_INT_ST_R {
61        L1_ICACHE0_PLD_ERR_INT_ST_R::new(((self.bits >> 7) & 1) != 0)
62    }
63    #[doc = "Bit 8 - The bit indicates the status of the interrupt of L1-ICache1 preload-operation error."]
64    #[inline(always)]
65    pub fn l1_icache1_pld_err_int_st(&self) -> L1_ICACHE1_PLD_ERR_INT_ST_R {
66        L1_ICACHE1_PLD_ERR_INT_ST_R::new(((self.bits >> 8) & 1) != 0)
67    }
68    #[doc = "Bit 9 - Reserved"]
69    #[inline(always)]
70    pub fn l1_icache2_pld_err_int_st(&self) -> L1_ICACHE2_PLD_ERR_INT_ST_R {
71        L1_ICACHE2_PLD_ERR_INT_ST_R::new(((self.bits >> 9) & 1) != 0)
72    }
73    #[doc = "Bit 10 - Reserved"]
74    #[inline(always)]
75    pub fn l1_icache3_pld_err_int_st(&self) -> L1_ICACHE3_PLD_ERR_INT_ST_R {
76        L1_ICACHE3_PLD_ERR_INT_ST_R::new(((self.bits >> 10) & 1) != 0)
77    }
78    #[doc = "Bit 11 - The bit indicates the status of the interrupt of L1-DCache preload-operation error."]
79    #[inline(always)]
80    pub fn l1_dcache_pld_err_int_st(&self) -> L1_DCACHE_PLD_ERR_INT_ST_R {
81        L1_DCACHE_PLD_ERR_INT_ST_R::new(((self.bits >> 11) & 1) != 0)
82    }
83    #[doc = "Bit 13 - The bit indicates the status of the interrupt of Cache sync-operation error."]
84    #[inline(always)]
85    pub fn sync_err_int_st(&self) -> SYNC_ERR_INT_ST_R {
86        SYNC_ERR_INT_ST_R::new(((self.bits >> 13) & 1) != 0)
87    }
88}
89#[cfg(feature = "impl-register-debug")]
90impl core::fmt::Debug for R {
91    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
92        f.debug_struct("SYNC_L1_CACHE_PRELOAD_INT_ST")
93            .field(
94                "l1_icache0_pld_done_int_st",
95                &format_args!("{}", self.l1_icache0_pld_done_int_st().bit()),
96            )
97            .field(
98                "l1_icache1_pld_done_int_st",
99                &format_args!("{}", self.l1_icache1_pld_done_int_st().bit()),
100            )
101            .field(
102                "l1_icache2_pld_done_int_st",
103                &format_args!("{}", self.l1_icache2_pld_done_int_st().bit()),
104            )
105            .field(
106                "l1_icache3_pld_done_int_st",
107                &format_args!("{}", self.l1_icache3_pld_done_int_st().bit()),
108            )
109            .field(
110                "l1_dcache_pld_done_int_st",
111                &format_args!("{}", self.l1_dcache_pld_done_int_st().bit()),
112            )
113            .field(
114                "sync_done_int_st",
115                &format_args!("{}", self.sync_done_int_st().bit()),
116            )
117            .field(
118                "l1_icache0_pld_err_int_st",
119                &format_args!("{}", self.l1_icache0_pld_err_int_st().bit()),
120            )
121            .field(
122                "l1_icache1_pld_err_int_st",
123                &format_args!("{}", self.l1_icache1_pld_err_int_st().bit()),
124            )
125            .field(
126                "l1_icache2_pld_err_int_st",
127                &format_args!("{}", self.l1_icache2_pld_err_int_st().bit()),
128            )
129            .field(
130                "l1_icache3_pld_err_int_st",
131                &format_args!("{}", self.l1_icache3_pld_err_int_st().bit()),
132            )
133            .field(
134                "l1_dcache_pld_err_int_st",
135                &format_args!("{}", self.l1_dcache_pld_err_int_st().bit()),
136            )
137            .field(
138                "sync_err_int_st",
139                &format_args!("{}", self.sync_err_int_st().bit()),
140            )
141            .finish()
142    }
143}
144#[cfg(feature = "impl-register-debug")]
145impl core::fmt::Debug for crate::generic::Reg<SYNC_L1_CACHE_PRELOAD_INT_ST_SPEC> {
146    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
147        core::fmt::Debug::fmt(&self.read(), f)
148    }
149}
150#[doc = "L1-Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
151pub struct SYNC_L1_CACHE_PRELOAD_INT_ST_SPEC;
152impl crate::RegisterSpec for SYNC_L1_CACHE_PRELOAD_INT_ST_SPEC {
153    type Ux = u32;
154}
155#[doc = "`read()` method returns [`sync_l1_cache_preload_int_st::R`](R) reader structure"]
156impl crate::Readable for SYNC_L1_CACHE_PRELOAD_INT_ST_SPEC {}
157#[doc = "`reset()` method sets SYNC_L1_CACHE_PRELOAD_INT_ST to value 0"]
158impl crate::Resettable for SYNC_L1_CACHE_PRELOAD_INT_ST_SPEC {
159    const RESET_VALUE: u32 = 0;
160}
esp32p4/cache/sync_l1_cache_preload_int_st.rs

esp32p4/cache/
sync_l1_cache_preload_int_st.rs
