esp32p4/cache/
l2_cache_debug_bus.rs

1#[doc = "Register `L2_CACHE_DEBUG_BUS` reader"]
2pub type R = crate::R<L2_CACHE_DEBUG_BUS_SPEC>;
3#[doc = "Register `L2_CACHE_DEBUG_BUS` writer"]
4pub type W = crate::W<L2_CACHE_DEBUG_BUS_SPEC>;
5#[doc = "Field `L2_CACHE_DEBUG_BUS` reader - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache."]
6pub type L2_CACHE_DEBUG_BUS_R = crate::FieldReader<u32>;
7#[doc = "Field `L2_CACHE_DEBUG_BUS` writer - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache."]
8pub type L2_CACHE_DEBUG_BUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    #[doc = "Bits 0:31 - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache."]
11    #[inline(always)]
12    pub fn l2_cache_debug_bus(&self) -> L2_CACHE_DEBUG_BUS_R {
13        L2_CACHE_DEBUG_BUS_R::new(self.bits)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("L2_CACHE_DEBUG_BUS")
20            .field(
21                "l2_cache_debug_bus",
22                &format_args!("{}", self.l2_cache_debug_bus().bits()),
23            )
24            .finish()
25    }
26}
27#[cfg(feature = "impl-register-debug")]
28impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_DEBUG_BUS_SPEC> {
29    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
30        core::fmt::Debug::fmt(&self.read(), f)
31    }
32}
33impl W {
34    #[doc = "Bits 0:31 - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache."]
35    #[inline(always)]
36    #[must_use]
37    pub fn l2_cache_debug_bus(&mut self) -> L2_CACHE_DEBUG_BUS_W<L2_CACHE_DEBUG_BUS_SPEC> {
38        L2_CACHE_DEBUG_BUS_W::new(self, 0)
39    }
40}
41#[doc = "Cache Tag/data memory content register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_debug_bus::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_debug_bus::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
42pub struct L2_CACHE_DEBUG_BUS_SPEC;
43impl crate::RegisterSpec for L2_CACHE_DEBUG_BUS_SPEC {
44    type Ux = u32;
45}
46#[doc = "`read()` method returns [`l2_cache_debug_bus::R`](R) reader structure"]
47impl crate::Readable for L2_CACHE_DEBUG_BUS_SPEC {}
48#[doc = "`write(|w| ..)` method takes [`l2_cache_debug_bus::W`](W) writer structure"]
49impl crate::Writable for L2_CACHE_DEBUG_BUS_SPEC {
50    type Safety = crate::Unsafe;
51    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
52    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
53}
54#[doc = "`reset()` method sets L2_CACHE_DEBUG_BUS to value 0x03cc"]
55impl crate::Resettable for L2_CACHE_DEBUG_BUS_SPEC {
56    const RESET_VALUE: u32 = 0x03cc;
57}
esp32p4/cache/l2_cache_debug_bus.rs

esp32p4/cache/
l2_cache_debug_bus.rs
