esp32p4/axi_dma/in_ch/in_int/
raw.rs1#[doc = "Register `RAW` reader"]
2pub type R = crate::R<RAW_SPEC>;
3#[doc = "Register `RAW` writer"]
4pub type W = crate::W<RAW_SPEC>;
5#[doc = "Field `IN_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
6pub type IN_DONE_R = crate::BitReader;
7#[doc = "Field `IN_DONE` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
8pub type IN_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `IN_SUC_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."]
10pub type IN_SUC_EOF_R = crate::BitReader;
11#[doc = "Field `IN_SUC_EOF` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."]
12pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `IN_ERR_EOF` reader - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved."]
14pub type IN_ERR_EOF_R = crate::BitReader;
15#[doc = "Field `IN_ERR_EOF` writer - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved."]
16pub type IN_ERR_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `IN_DSCR_ERR` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0."]
18pub type IN_DSCR_ERR_R = crate::BitReader;
19#[doc = "Field `IN_DSCR_ERR` writer - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0."]
20pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `IN_DSCR_EMPTY` reader - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0."]
22pub type IN_DSCR_EMPTY_R = crate::BitReader;
23#[doc = "Field `IN_DSCR_EMPTY` writer - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0."]
24pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `INFIFO_L1_OVF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
26pub type INFIFO_L1_OVF_R = crate::BitReader;
27#[doc = "Field `INFIFO_L1_OVF` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
28pub type INFIFO_L1_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `INFIFO_L1_UDF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
30pub type INFIFO_L1_UDF_R = crate::BitReader;
31#[doc = "Field `INFIFO_L1_UDF` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
32pub type INFIFO_L1_UDF_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `INFIFO_L2_OVF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
34pub type INFIFO_L2_OVF_R = crate::BitReader;
35#[doc = "Field `INFIFO_L2_OVF` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
36pub type INFIFO_L2_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `INFIFO_L2_UDF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
38pub type INFIFO_L2_UDF_R = crate::BitReader;
39#[doc = "Field `INFIFO_L2_UDF` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
40pub type INFIFO_L2_UDF_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `INFIFO_L3_OVF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
42pub type INFIFO_L3_OVF_R = crate::BitReader;
43#[doc = "Field `INFIFO_L3_OVF` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
44pub type INFIFO_L3_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `INFIFO_L3_UDF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
46pub type INFIFO_L3_UDF_R = crate::BitReader;
47#[doc = "Field `INFIFO_L3_UDF` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
48pub type INFIFO_L3_UDF_W<'a, REG> = crate::BitWriter<'a, REG>;
49impl R {
50 #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
51 #[inline(always)]
52 pub fn in_done(&self) -> IN_DONE_R {
53 IN_DONE_R::new((self.bits & 1) != 0)
54 }
55 #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."]
56 #[inline(always)]
57 pub fn in_suc_eof(&self) -> IN_SUC_EOF_R {
58 IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0)
59 }
60 #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved."]
61 #[inline(always)]
62 pub fn in_err_eof(&self) -> IN_ERR_EOF_R {
63 IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0)
64 }
65 #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0."]
66 #[inline(always)]
67 pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R {
68 IN_DSCR_ERR_R::new(((self.bits >> 3) & 1) != 0)
69 }
70 #[doc = "Bit 4 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0."]
71 #[inline(always)]
72 pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R {
73 IN_DSCR_EMPTY_R::new(((self.bits >> 4) & 1) != 0)
74 }
75 #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
76 #[inline(always)]
77 pub fn infifo_l1_ovf(&self) -> INFIFO_L1_OVF_R {
78 INFIFO_L1_OVF_R::new(((self.bits >> 5) & 1) != 0)
79 }
80 #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
81 #[inline(always)]
82 pub fn infifo_l1_udf(&self) -> INFIFO_L1_UDF_R {
83 INFIFO_L1_UDF_R::new(((self.bits >> 6) & 1) != 0)
84 }
85 #[doc = "Bit 7 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
86 #[inline(always)]
87 pub fn infifo_l2_ovf(&self) -> INFIFO_L2_OVF_R {
88 INFIFO_L2_OVF_R::new(((self.bits >> 7) & 1) != 0)
89 }
90 #[doc = "Bit 8 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
91 #[inline(always)]
92 pub fn infifo_l2_udf(&self) -> INFIFO_L2_UDF_R {
93 INFIFO_L2_UDF_R::new(((self.bits >> 8) & 1) != 0)
94 }
95 #[doc = "Bit 9 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
96 #[inline(always)]
97 pub fn infifo_l3_ovf(&self) -> INFIFO_L3_OVF_R {
98 INFIFO_L3_OVF_R::new(((self.bits >> 9) & 1) != 0)
99 }
100 #[doc = "Bit 10 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
101 #[inline(always)]
102 pub fn infifo_l3_udf(&self) -> INFIFO_L3_UDF_R {
103 INFIFO_L3_UDF_R::new(((self.bits >> 10) & 1) != 0)
104 }
105}
106#[cfg(feature = "impl-register-debug")]
107impl core::fmt::Debug for R {
108 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
109 f.debug_struct("RAW")
110 .field("in_done", &format_args!("{}", self.in_done().bit()))
111 .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
112 .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
113 .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
114 .field(
115 "in_dscr_empty",
116 &format_args!("{}", self.in_dscr_empty().bit()),
117 )
118 .field(
119 "infifo_l1_ovf",
120 &format_args!("{}", self.infifo_l1_ovf().bit()),
121 )
122 .field(
123 "infifo_l1_udf",
124 &format_args!("{}", self.infifo_l1_udf().bit()),
125 )
126 .field(
127 "infifo_l2_ovf",
128 &format_args!("{}", self.infifo_l2_ovf().bit()),
129 )
130 .field(
131 "infifo_l2_udf",
132 &format_args!("{}", self.infifo_l2_udf().bit()),
133 )
134 .field(
135 "infifo_l3_ovf",
136 &format_args!("{}", self.infifo_l3_ovf().bit()),
137 )
138 .field(
139 "infifo_l3_udf",
140 &format_args!("{}", self.infifo_l3_udf().bit()),
141 )
142 .finish()
143 }
144}
145#[cfg(feature = "impl-register-debug")]
146impl core::fmt::Debug for crate::generic::Reg<RAW_SPEC> {
147 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
148 core::fmt::Debug::fmt(&self.read(), f)
149 }
150}
151impl W {
152 #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
153 #[inline(always)]
154 #[must_use]
155 pub fn in_done(&mut self) -> IN_DONE_W<RAW_SPEC> {
156 IN_DONE_W::new(self, 0)
157 }
158 #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."]
159 #[inline(always)]
160 #[must_use]
161 pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<RAW_SPEC> {
162 IN_SUC_EOF_W::new(self, 1)
163 }
164 #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved."]
165 #[inline(always)]
166 #[must_use]
167 pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<RAW_SPEC> {
168 IN_ERR_EOF_W::new(self, 2)
169 }
170 #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0."]
171 #[inline(always)]
172 #[must_use]
173 pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<RAW_SPEC> {
174 IN_DSCR_ERR_W::new(self, 3)
175 }
176 #[doc = "Bit 4 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0."]
177 #[inline(always)]
178 #[must_use]
179 pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<RAW_SPEC> {
180 IN_DSCR_EMPTY_W::new(self, 4)
181 }
182 #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
183 #[inline(always)]
184 #[must_use]
185 pub fn infifo_l1_ovf(&mut self) -> INFIFO_L1_OVF_W<RAW_SPEC> {
186 INFIFO_L1_OVF_W::new(self, 5)
187 }
188 #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
189 #[inline(always)]
190 #[must_use]
191 pub fn infifo_l1_udf(&mut self) -> INFIFO_L1_UDF_W<RAW_SPEC> {
192 INFIFO_L1_UDF_W::new(self, 6)
193 }
194 #[doc = "Bit 7 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
195 #[inline(always)]
196 #[must_use]
197 pub fn infifo_l2_ovf(&mut self) -> INFIFO_L2_OVF_W<RAW_SPEC> {
198 INFIFO_L2_OVF_W::new(self, 7)
199 }
200 #[doc = "Bit 8 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
201 #[inline(always)]
202 #[must_use]
203 pub fn infifo_l2_udf(&mut self) -> INFIFO_L2_UDF_W<RAW_SPEC> {
204 INFIFO_L2_UDF_W::new(self, 8)
205 }
206 #[doc = "Bit 9 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
207 #[inline(always)]
208 #[must_use]
209 pub fn infifo_l3_ovf(&mut self) -> INFIFO_L3_OVF_W<RAW_SPEC> {
210 INFIFO_L3_OVF_W::new(self, 9)
211 }
212 #[doc = "Bit 10 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
213 #[inline(always)]
214 #[must_use]
215 pub fn infifo_l3_udf(&mut self) -> INFIFO_L3_UDF_W<RAW_SPEC> {
216 INFIFO_L3_UDF_W::new(self, 10)
217 }
218}
219#[doc = "Raw status interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
220pub struct RAW_SPEC;
221impl crate::RegisterSpec for RAW_SPEC {
222 type Ux = u32;
223}
224#[doc = "`read()` method returns [`raw::R`](R) reader structure"]
225impl crate::Readable for RAW_SPEC {}
226#[doc = "`write(|w| ..)` method takes [`raw::W`](W) writer structure"]
227impl crate::Writable for RAW_SPEC {
228 type Safety = crate::Unsafe;
229 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
230 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
231}
232#[doc = "`reset()` method sets RAW to value 0"]
233impl crate::Resettable for RAW_SPEC {
234 const RESET_VALUE: u32 = 0;
235}