esp32p4/ahb_dma/ch/
in_conf0.rs

1#[doc = "Register `IN_CONF0` reader"]
2pub type R = crate::R<IN_CONF0_SPEC>;
3#[doc = "Register `IN_CONF0` writer"]
4pub type W = crate::W<IN_CONF0_SPEC>;
5#[doc = "Field `IN_RST` reader - This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer."]
6pub type IN_RST_R = crate::BitReader;
7#[doc = "Field `IN_RST` writer - This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer."]
8pub type IN_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `IN_LOOP_TEST` reader - reserved"]
10pub type IN_LOOP_TEST_R = crate::BitReader;
11#[doc = "Field `IN_LOOP_TEST` writer - reserved"]
12pub type IN_LOOP_TEST_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `INDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
14pub type INDSCR_BURST_EN_R = crate::BitReader;
15#[doc = "Field `INDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
16pub type INDSCR_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `IN_DATA_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
18pub type IN_DATA_BURST_EN_R = crate::BitReader;
19#[doc = "Field `IN_DATA_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
20pub type IN_DATA_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `MEM_TRANS_EN` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA."]
22pub type MEM_TRANS_EN_R = crate::BitReader;
23#[doc = "Field `MEM_TRANS_EN` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA."]
24pub type MEM_TRANS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `IN_ETM_EN` reader - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."]
26pub type IN_ETM_EN_R = crate::BitReader;
27#[doc = "Field `IN_ETM_EN` writer - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."]
28pub type IN_ETM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 0 - This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer."]
31    #[inline(always)]
32    pub fn in_rst(&self) -> IN_RST_R {
33        IN_RST_R::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1 - reserved"]
36    #[inline(always)]
37    pub fn in_loop_test(&self) -> IN_LOOP_TEST_R {
38        IN_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
41    #[inline(always)]
42    pub fn indscr_burst_en(&self) -> INDSCR_BURST_EN_R {
43        INDSCR_BURST_EN_R::new(((self.bits >> 2) & 1) != 0)
44    }
45    #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
46    #[inline(always)]
47    pub fn in_data_burst_en(&self) -> IN_DATA_BURST_EN_R {
48        IN_DATA_BURST_EN_R::new(((self.bits >> 3) & 1) != 0)
49    }
50    #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA."]
51    #[inline(always)]
52    pub fn mem_trans_en(&self) -> MEM_TRANS_EN_R {
53        MEM_TRANS_EN_R::new(((self.bits >> 4) & 1) != 0)
54    }
55    #[doc = "Bit 5 - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."]
56    #[inline(always)]
57    pub fn in_etm_en(&self) -> IN_ETM_EN_R {
58        IN_ETM_EN_R::new(((self.bits >> 5) & 1) != 0)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("IN_CONF0")
65            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
66            .field(
67                "in_loop_test",
68                &format_args!("{}", self.in_loop_test().bit()),
69            )
70            .field(
71                "indscr_burst_en",
72                &format_args!("{}", self.indscr_burst_en().bit()),
73            )
74            .field(
75                "in_data_burst_en",
76                &format_args!("{}", self.in_data_burst_en().bit()),
77            )
78            .field(
79                "mem_trans_en",
80                &format_args!("{}", self.mem_trans_en().bit()),
81            )
82            .field("in_etm_en", &format_args!("{}", self.in_etm_en().bit()))
83            .finish()
84    }
85}
86#[cfg(feature = "impl-register-debug")]
87impl core::fmt::Debug for crate::generic::Reg<IN_CONF0_SPEC> {
88    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
89        core::fmt::Debug::fmt(&self.read(), f)
90    }
91}
92impl W {
93    #[doc = "Bit 0 - This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer."]
94    #[inline(always)]
95    #[must_use]
96    pub fn in_rst(&mut self) -> IN_RST_W<IN_CONF0_SPEC> {
97        IN_RST_W::new(self, 0)
98    }
99    #[doc = "Bit 1 - reserved"]
100    #[inline(always)]
101    #[must_use]
102    pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<IN_CONF0_SPEC> {
103        IN_LOOP_TEST_W::new(self, 1)
104    }
105    #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
106    #[inline(always)]
107    #[must_use]
108    pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<IN_CONF0_SPEC> {
109        INDSCR_BURST_EN_W::new(self, 2)
110    }
111    #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
112    #[inline(always)]
113    #[must_use]
114    pub fn in_data_burst_en(&mut self) -> IN_DATA_BURST_EN_W<IN_CONF0_SPEC> {
115        IN_DATA_BURST_EN_W::new(self, 3)
116    }
117    #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA."]
118    #[inline(always)]
119    #[must_use]
120    pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<IN_CONF0_SPEC> {
121        MEM_TRANS_EN_W::new(self, 4)
122    }
123    #[doc = "Bit 5 - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."]
124    #[inline(always)]
125    #[must_use]
126    pub fn in_etm_en(&mut self) -> IN_ETM_EN_W<IN_CONF0_SPEC> {
127        IN_ETM_EN_W::new(self, 5)
128    }
129}
130#[doc = "Configure 0 register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
131pub struct IN_CONF0_SPEC;
132impl crate::RegisterSpec for IN_CONF0_SPEC {
133    type Ux = u32;
134}
135#[doc = "`read()` method returns [`in_conf0::R`](R) reader structure"]
136impl crate::Readable for IN_CONF0_SPEC {}
137#[doc = "`write(|w| ..)` method takes [`in_conf0::W`](W) writer structure"]
138impl crate::Writable for IN_CONF0_SPEC {
139    type Safety = crate::Unsafe;
140    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
141    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
142}
143#[doc = "`reset()` method sets IN_CONF0 to value 0"]
144impl crate::Resettable for IN_CONF0_SPEC {
145    const RESET_VALUE: u32 = 0;
146}
esp32p4/ahb_dma/ch/in_conf0.rs

esp32p4/ahb_dma/ch/
in_conf0.rs
