esp32p4/spi1/
clock.rs

1#[doc = "Register `CLOCK` reader"]
2pub type R = crate::R<CLOCK_SPEC>;
3#[doc = "Register `CLOCK` writer"]
4pub type W = crate::W<CLOCK_SPEC>;
5#[doc = "Field `CLKCNT_L` reader - In the master mode it must be equal to spi_mem_clkcnt_N."]
6pub type CLKCNT_L_R = crate::FieldReader;
7#[doc = "Field `CLKCNT_L` writer - In the master mode it must be equal to spi_mem_clkcnt_N."]
8pub type CLKCNT_L_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `CLKCNT_H` reader - In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)."]
10pub type CLKCNT_H_R = crate::FieldReader;
11#[doc = "Field `CLKCNT_H` writer - In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)."]
12pub type CLKCNT_H_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `CLKCNT_N` reader - In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)"]
14pub type CLKCNT_N_R = crate::FieldReader;
15#[doc = "Field `CLKCNT_N` writer - In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)"]
16pub type CLKCNT_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17#[doc = "Field `CLK_EQU_SYSCLK` reader - reserved"]
18pub type CLK_EQU_SYSCLK_R = crate::BitReader;
19#[doc = "Field `CLK_EQU_SYSCLK` writer - reserved"]
20pub type CLK_EQU_SYSCLK_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bits 0:7 - In the master mode it must be equal to spi_mem_clkcnt_N."]
23    #[inline(always)]
24    pub fn clkcnt_l(&self) -> CLKCNT_L_R {
25        CLKCNT_L_R::new((self.bits & 0xff) as u8)
26    }
27    #[doc = "Bits 8:15 - In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)."]
28    #[inline(always)]
29    pub fn clkcnt_h(&self) -> CLKCNT_H_R {
30        CLKCNT_H_R::new(((self.bits >> 8) & 0xff) as u8)
31    }
32    #[doc = "Bits 16:23 - In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)"]
33    #[inline(always)]
34    pub fn clkcnt_n(&self) -> CLKCNT_N_R {
35        CLKCNT_N_R::new(((self.bits >> 16) & 0xff) as u8)
36    }
37    #[doc = "Bit 31 - reserved"]
38    #[inline(always)]
39    pub fn clk_equ_sysclk(&self) -> CLK_EQU_SYSCLK_R {
40        CLK_EQU_SYSCLK_R::new(((self.bits >> 31) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("CLOCK")
47            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
48            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
49            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
50            .field(
51                "clk_equ_sysclk",
52                &format_args!("{}", self.clk_equ_sysclk().bit()),
53            )
54            .finish()
55    }
56}
57#[cfg(feature = "impl-register-debug")]
58impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
59    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
60        core::fmt::Debug::fmt(&self.read(), f)
61    }
62}
63impl W {
64    #[doc = "Bits 0:7 - In the master mode it must be equal to spi_mem_clkcnt_N."]
65    #[inline(always)]
66    #[must_use]
67    pub fn clkcnt_l(&mut self) -> CLKCNT_L_W<CLOCK_SPEC> {
68        CLKCNT_L_W::new(self, 0)
69    }
70    #[doc = "Bits 8:15 - In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)."]
71    #[inline(always)]
72    #[must_use]
73    pub fn clkcnt_h(&mut self) -> CLKCNT_H_W<CLOCK_SPEC> {
74        CLKCNT_H_W::new(self, 8)
75    }
76    #[doc = "Bits 16:23 - In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)"]
77    #[inline(always)]
78    #[must_use]
79    pub fn clkcnt_n(&mut self) -> CLKCNT_N_W<CLOCK_SPEC> {
80        CLKCNT_N_W::new(self, 16)
81    }
82    #[doc = "Bit 31 - reserved"]
83    #[inline(always)]
84    #[must_use]
85    pub fn clk_equ_sysclk(&mut self) -> CLK_EQU_SYSCLK_W<CLOCK_SPEC> {
86        CLK_EQU_SYSCLK_W::new(self, 31)
87    }
88}
89#[doc = "SPI1 clock division control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
90pub struct CLOCK_SPEC;
91impl crate::RegisterSpec for CLOCK_SPEC {
92    type Ux = u32;
93}
94#[doc = "`read()` method returns [`clock::R`](R) reader structure"]
95impl crate::Readable for CLOCK_SPEC {}
96#[doc = "`write(|w| ..)` method takes [`clock::W`](W) writer structure"]
97impl crate::Writable for CLOCK_SPEC {
98    type Safety = crate::Unsafe;
99    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
100    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
101}
102#[doc = "`reset()` method sets CLOCK to value 0x0003_0103"]
103impl crate::Resettable for CLOCK_SPEC {
104    const RESET_VALUE: u32 = 0x0003_0103;
105}
esp32p4/spi1/clock.rs

esp32p4/spi1/
clock.rs
